T2080 motherboard ASLEEP signal LED stays ON, it seems that the CPU is asleep

[robertoinnocent]

Our open hardware T2080 Powerboard Tyche  ( schematics and pcb sources) doesn't reach de boot loader ( u-boot).

Tests on the NAND programming were successful. We dumped the memory to a file and then we verified that U-Boot was flashed correctly. However, when selecting the switches to boot from NAND, the prototype board does not seem to do any booting. In fact, the ASLEEP signal LED stays ON, and from the power supply bank, it seems that the CPU is asleep.

The DDR cannot be initialised in any way. We do not have any further information about this initialisation at the moment because only very few simple SRAM tests can be run on the board.

The output on the serial, but the text is illegible, on devkit the output is readable and is this:
Core0-Thread0: Welcome to CodeWarrior!

Powerboard Tyche serial output on the Oscilloscope

Powerboard Tyche serial output on the Oscilloscope

As our PowerBoard Tyche have not the third switch like the NXP T2080-RDB Devkit a few additional resistors were required to setup correctly the board to be able to switch on the Code Warrior debug connected to our Powerboard Tyche.

additional resistors due to the switches differences from devkit

[robertoinnocent]

We observe on serial only a baud rate of 14-15Khjz instead of 1115KHz of T2080 Devkit 

[yipingwang]

Check for HRESET_B, if negated it implies that RCW loading is complete.

Check for ASLEEP, if low it means that PBI is complete.

According to the waveform or your serial, it seems that the serial has already been initialized, it means u-boot has been loaded.

Please refer to the following step by step user manual to debug u-boot from NAND flash.

https://community.nxp.com/t5/CodeWarrior-Development-Tools/CodeWarrior-U-Boot-Debugging/ta-p/1121398

[robertoinnocent]

Thanks for your answer,. but the problem is before the booting to u-boot.

In fact we have found difference on signals on boot process between oujr motherboard and the T2080'RDB. and in fact we have done few updates on our CPLD to create thje right sequences.

In fact in the pendrive provided with the T2080 Devkit we have even few file related to the CPLD of T2080RDB Devkit , the soruce in Verilog that is t2080pcie - V1.3.v look corrupted.

Could you provide me the not corrupted file?

Thanks

[robertoinnocent]

Found files in  https://www.nxp.com/design/design-center/software/qoriq-developer-resources/qoriq-t2080-development-...

[robertoinnocent]

We are thinking to review the CPLD program of Lattice LCMXO640C-3TN100C FPGA and the RCW data.

[yipingwang]

In u-boot source code folder board/freescale/t208xrdb, please check whether you have configured RCW file t2080_nand_rcw.cfg and PBI command file t2080_pbi.cfg according to your custom board.

[robertoinnocent]

But in the "Power-on reset sequence" looks it arrive at at POR seuquence 8 ( pag 195 T2080RM.pdf ) so uboot is not already loaded