T2080 : Unable to load RCW from Flash

[Arathi]

Hi NXP Support Team,

We have T2080 processor with Artix7 FPGA to interface IFC to NOR-flash. We faced issue while reading flash ID (from T2080) in the hardcoded boot mode but we are able to read the contents of the flash(this implies we are able to read but we are unable to write to flash)

Since we have Artix7 FPGA, using microblaze we were able to read flash ID, read and write to flash, we have written RCW in the first location of flash. 

Now we have changed the boot mode to NOR flash by configuring cfg_rcw_src[8:0] to 1C8 (T2080 Reference Manual Table 4-8. RCW source encodings).
We are expecting the IFC controller to read the RCW from the flash. But the IFC is not issuing address transactions.

While trying to boot from NOR flash since it is unable to read, it unable to load RCW from flash, At the same time HRESET is always LOW(Processor is in Reset)

Even clock from IFC is not stable.(Clock is not continuous, RCW state timings are not as per Table 4-9. RCW state timing of T2080 RM)

Attaching the required screenshots of IFC_CLK_0 at different instance with same configurations for your reference

Please help us regarding the same.  

Thanks,
Arathi

[yipingwang]

RCW is programmed at the bottom of NOR flash. For e.g. for a 16MB NOR (0x00_0000 to 0xff_ffff) program at 0x00_0000.
Default Boot Translation window is mapped in 8 Mbytes at 0x0_FF80_0000 to 0x0_FFFF_FFFF. When each core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. First fetch is a burst at 0x0_FFFF_FFC0 and first instruction is executed at 0x0_FFFF_FFFC.
U-boot should be programmed at top of flash.


Probe the Chip Select and Clock of the NOR flash and check their status with respect to the assertion of the PORESET signal.