T2080 SRIO NWRITE/NREAD, Two T2080s, No Switches

cancel
Showing results for 
Search instead for 
Did you mean: 

T2080 SRIO NWRITE/NREAD, Two T2080s, No Switches

950 Views
jameshorton
Contributor II

Config is:

2 T2080s with a 3' cable

No switches

GCCSR is 0xE0000000 on both T2080s

Netcomm SW with INTEGRITY 1142

ESCSR ix 0x2 on both ( can also for a retrain successfully when errors occur).

Base Device IDs are statically defined (0xF1 and 0xF5)

There was no host enumeration process performed. Assuming static IDs were setup by each endpoint (which I did). Just going endpoint to endpoint on port zero.

Execution is:

I got a solid link at power up/init with no errors.  ESCSR is 0x2 which is a good start.  I have a single outbound, and a single inbound window on each T2080.  When I perform a NWRITE from one's outbound window, I get error bits on both sides.

The LTLEDSCR gets and IER bit set on the sender side (outbound) and a ITD set on the receiver side (inbound).

I've repeated a similar test with an Altera FPGA doing an NWRITE to my T2080.  We used a signal tap to see data move on the bus. We saw 0xDEABEEF with the correct device ids. The T2080 receiver gets the same ITD.  Input and output transmission errors get set on the Altera FPGA sender.

We tried two Altera FPGAs can nwrite/nread back and forth fine.

Labels (1)
Tags (2)
0 Kudos
2 Replies

324 Views
ufedor
NXP TechSupport
NXP TechSupport

The issue could be caused by several reasons - refer to the QorIQ T2080 Reference Manual, Table 21-13. Hardware Errors For NWrite, NWrite_r, and Unsupported Atomic Test-and-Swap Transactions.

Please provide for both T2080 parties:

1) LAW CCSR registers dumps

2) complete SRIO CCSR registers dumps immediately after initialization and after attempting the NWRITE transaction

3) which T2080 SOC address is written to initiate the SRIO NWRITE transaction?

0 Kudos

324 Views
lifengwang
Contributor I

I have the same problem? Have you solved? Can you help me?thinks

0 Kudos