Hope this post finds you well,
The T2080 as I said in my previously reply has 512 KB CoreNet platform cache (CPC).
The SRAM mode registers enable and configure the CPC to be used as SRAM space.
We currently do not have an example to do it, nevertheless here is the process to do it:
You can do it using the CPC_CPCSRCR0 register, this register configures the CPC when it is used as
SRAM.
Please refer to the 8.3.1.1 SRAM Mode Registers located at page 295 of the QorIQ T2080 Reference Manual, Rev. 4, 04/2021
SRAM mode is enabled by CPCSRCR0[SRAMEN], the size of the SRAM address space
is configured by CPCSRCR0[SRAMSZ], and the base address of the SRAM address
space is specified using CPCSRCR0[SRBARL] and CPCSRCR1[SRBARU].
Have a great day.
BR,
Hector