T2080 SGMII vs TI DP83867 PHY

[jerzdy_rail_mil]

Hi,

I faced problem with SGMII auto-negotiation on T2080

My hardware is NXP T2080 SGMII <-> TI DP83867 PHY.

Please consider below sniped of the u-boot code :

(read ability, set according it SGMII Link Timer and restart AN)

drivers/net/fm/eth.c:

/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);

if (sgmii_2500) {
/* Adjust link timer for 2.5G SGMII,
* 1.6 ms in units of 3.2 ns:
* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
*/
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
} else {
/* Adjust link timer for SGMII,
* 1.6 ms in units of 8 ns:
* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
*/
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
}

/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);

/* Dev ability according to SGMII specification */
value = PHY_SGMII_DEV_ABILITY_SGMII;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);

if (sgmii_2500) {
/* Adjust link timer for 2.5G SGMII,
* 1.6 ms in units of 3.2 ns:
* 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
*/
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
} else {
/* Adjust link timer for SGMII,
* 1.6 ms in units of 8 ns:
* 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
*/
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
}

/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);

But it doesn't work (even TI PHY has increased SGMII Autoneg timer up to 16 ms) - no SGMII link,

AN failed.

If T2080 SGMII Link Timer is set also on 0x7a120 like for 2.5G SGMII, AN finished with success.

I have few question :

1. I which unit is notated SGMII Link Timer?

2. Our HW configuration uses 100 MHz SERDES reference clock. 

SRDS_PRTCL_S1 = A2, SRDS_PRTCL_S2 = 16, 

SRDS_PLL_REF_CLK_SEL_S1 = 100MHz, SRDS_PLL_REF_CLK_SEL_S2 = 100MHz

How behaves SGMII Link Timer? Timer tick will be 10 ns?

3. What is suggested value of the SGMII Link Timer for 1.25G SGMII?

Best regards,

Jerzy Dyrda

[jerzdy_rail_mil]

Thank you for your answer.

(..) You can set it to a different value if the PHY (..)

And here is a problem. Code for SGMII Link Timer is a general function which

doesn't know anything about type of PHY. The value of the SGMII Link Timer

is set a priori during interface initialization.

BTW. Above code is a Freescale code. I assume that someone check/test it.

And one more complaints. The same PHY works fine with P1010 even without

extending SGMII timer on PHY side. It looks like that something wrong happened

while auto-negotiation.

Best regards,

Jerzy Dyrda

[bpe]

The timer initialized by this code is defined in IEEE 802.3 Section 37.3.1.4
and updated by SGMII Specification to have the value of 1.6 ms for the purpose of
SGMII interface. NXP does not suggest any value for it except for the one
defined in the specification. You can set it to a different value if the PHY
requires that, consult at the PHY documentation or contact it's manufacturer.
The timer tick duration only depends on the interface baud and not on the reference
clock.

Hope this helps,
Platon