T2080 Power and reset

[Har_ika30]

Hi,
I am using T2080 Processor in my design

PORESET_B : Main board reset
HRESET_B : Push-button switch

FPGA is being used for power, reset sequencing and for IFC AD BUS De-latching

1) How PORESET_B will be related to HRESET_B on Power On condition?

2) When HRESET_B be considered as input/output? what is the state of HRESET when PORESET in  Low?

3) In order to boot Processor from flash what will be power on reset sequencing? Is there any reset timing requirements?

Thanks

Harika

[Hector_Villarruel]

Hello @Har_ika30 

Regarding to your questions:

1) How PORESET_B will be related to HRESET_B on Power On condition?

I will refer to the section 4.6.1 Power-on reset sequence located on the reference manual of the device.

After the negation of PORESET_B, the reset control logic begins cycling the device
through its full reset and RCW configuration process. The chip asserts HRESET_B
throughout the power-on reset process, including RCW configuration.

Reset and RCW configuration time varies depending on the configuration source and SYSCLK frequency.

The device requires PORESET to be asserted before all power supplies are applied, and PORESET must be asserted for at least 1 ms (datasheet requirement).

2) When HRESET_B be considered as input/output? what is the state of HRESET when PORESET in  Low?

Please note HRESET_B is considered as an input/output on QorIQ T2080 Data Sheet, Rev. 3, 03/2018.

Your second questions depends on how did you take the reference, nevertheless please note that the device begins driving HRESET_B asserted after sampling the assertion of
PORESET_B.

We highly recommend you to check the 4.6.1 Power-on reset sequence of QorIQ T2080 Reference Manual, Rev. 4, 04/2021 

3) In order to boot Processor from flash what will be power on reset sequencing? Is there any reset timing requirements?

Regarding to your first question:

Please note that If the FCM is selected as the boot ROM controller from power-on-reset configuration, the IFC automatically loads up to 8 KB of boot code from BANK0 to the NAND FCM buffer
RAM depending on the RCW load or BOOT load indication.

Regarding to your second question:

Yes, there is a timing requirements please see the attached image in reference.

Have a great day.

Hector Villarruel

[Har_ika30]

Hi Hector,

Thanks for prompt response.

I continue to be confused by the concepts "assertion" and "negation."

According to my understanding, Assertion can either be active high or active low depending on the signal, and Negation are active low.

Assuming that we have used FPGA in my design for power and reset sequencing.
1) Until all power supplies are operational, the PORESET_B will be in the active low (reset) state; after that, it will be released to the active high (out of reset) state.
2) Even though PORESET_B signal is in Reset, since HRESET_B signal is an open drain(output signal), and it will always be high.

As per the attached image
1) we are Asserting processor PORESET_B (Active High) on following conditions
--->When all power rails are up
--->when HRESET_B from the COP Header or RESET_REQ from the processor are requested
2) we are Asserting processor HRESET_B (Active High) on following conditions
---> When COP Header SRESET is asserted, HRESET_B will also be asserted.

Is this the correct procedure for processor power-on reset?

[Hector_Villarruel]

Hello @Har_ika30 

Regarding to your last question:

"Is this the correct procedure for processor power-on reset?

Yes, that will be one of the appropriate procedures for processor power-on reset.

Have a great day.

Best Regards,

Hector Villarruel