Hi Team,
We are using T2080 in our design, We have few queries regards to Power sequence,
Are there any power sequence /timing requirement between VDD Core Voltage and Serdes Voltage?
That is, VDD and SVDD,XVDD
The datasheet doesn't recommend any sequence between these,
In our design, we have followed this way,
1) VDD Core
2) VDD 1V8 (OVDD,DVDD,CVDD)
3) VCC 1V35 (G1VDD DDR and XVDD)
4) VCC 1V0 (SVDD)
Each ramp up timing is within 5-10ms i.e., With respect to each rail there is a delay of 5-10ms
Is this acceptable for T2080.
Or Is there a requirement for VDD and SVDD and XVDD Ramp up timing?
Thanks