T2080 PLL configuration for 1000BaseKX

[scottgerhold]

When using SerDes protocol F236, we want to use SG2 as 1000BaseKX. All lanes of SerDes bank 1 are mapped to PLL1 per Table 19-1 of the Reference Manual. PCIe4 is capable of Gen3 in this case, and PCIe1, 2 and 3 are all mapped to PLL1 also. 

Per the section 19.4.2 SerDesxPLLnCR0, DLYDIV_SEL must be set to 01 to enable FRATE_SEL/16. The input PLL1 reference clock is set to 100MHz. 

The questions are

1. Since changing DLYDIV_SEL is reconfiguring the PLL, must the PLL Reset and Reconfiguration process defined in 19.6.4.3 be followed?
2. Must all PCIe controllers "attached" to PLL1 be disabled before changing DLYDIV_SEL for PLL1?
3. Does changing this setting impact the operation of the PCIe interfaces on that PLL1 after the process is followed?

[RachelGomez123]

Yes, changing DLYDIV_SEL will reconfigure the PLL1, and thus the PLL Reset and Reconfiguration process defined in section 19.6.4.3 of the Reference Manual must be followed. This process ensures that the PLL1 is properly reset and reconfigured with the new settings.

It is recommended to disable all PCIe controllers attached to PLL1 before changing DLYDIV_SEL for PLL1. This is to prevent any data loss or corruption during the reconfiguration process. It is also important to ensure that the SerDes protocol F236 is properly configured to use SG2 as 1000BaseKX, as any misconfiguration can lead to operational issues.

Changing DLYDIV_SEL for PLL1 should not impact the operation of the PCIe interfaces on that PLL1 after the process is followed. However, it is recommended to perform thorough testing and validation of the system after any changes are made to ensure that there are no unexpected issues.

Regards,

Rachel Gomez

[mrudangshelat-13]

Hi @scottgerhold,

Please refer to section# 19.6.1.2 mentioned in the T2080RM.

Regards,
Mrudang

[scottgerhold]

I am aware of section 19.6.1.2. My question is not answered in that section. 19.6.1.2 tells you that you need to set DLYDIV_SEL to 01, as does 19.4.2. But as I referenced above, section 19.6.4.3, which covers reconfiguring the PLLs, states that we are supposed to disable ALL lanes when the PLL is reconfigured. My question is whether or not changing DLYDIV_SEL is considered to be reconfiguring the PLL in which case I need to turn off all interfaces in SerDes1 using PLL1, since SerDes1_PLL1CR0 could be impacting all lanes in SerDes1 in this case. Or does the DLYDIV_SEL parameter just change the clocking for the lanes associated with SGMII/1GBaseKX or maybe just turning on an optional clock output to the 1000BaseKX circuitry?