Are both slaves going to operate in synchronous mode? Generally we have seen Flashes operate in asynchronous mode. The timing of signals, like ALE, WLE etc, are to be programmed for every chip select. For example, please refer to "Figure 13-18. BCTL signal in NAND read followed by any other operation" and "Figure 13-19. BCTL signal in NOR read followed by any other operation" of T2080RM Rev 4. All the timings are shown with respect to ip_clk. ip_clk is platform clock/2. This is constant for a given platform frequency.
If both slaves are synchronous, there are the two IFC_CLK available in T2080. You can configure it to output 100MHz and use onboard clock divider to reduce it to 20MHz for second slave.
If both slaves are synchronous, and you do not want to use onboard frequecny divider, then you can try the following method:
The IFC has IFC_CCR to configure the frequency of the IFC_CLK. You can change the value of IFC_CCR every time you access different slave. This has to be done very carefully. For example if you are using Linux and have two seperate device drivers (say DriverA and DriverB), you need to ensure:
1) All the access to slave A is routed through DriverA and all the access to slave B is routed through DriverB
2) You will have to use some semaphores. If DriverA is operating, it'll take the "lock" and unlock after all the operations are completed. DriverB will always check "lock" before operating. If the lock has been taken by DriverA, DriverB will have to wait till DriverA releases the "lock".
3) After changing the IFC_CCR, wait for atleast 1us for glitch free operations.
