T2080 MDIO register spaces access

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T2080 MDIO register spaces access

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xabiven
Contributor II

Hello,

I'm using a T2080 processor with 0x66 SERDES configuration on SD1 bloc.

So, I have four "10 Gigabit ports" : two used in XFI mode, connected to Ethernet PHYs for 10GBASE-T support, and two directly connected to a backplane's interface.

The two Ethernet PHYs are connected to the EMI2 bus for configuration. They are using 0x0 and 0x1 addresses and respond without issue to all mdc/mdio commands.

I'd like to access to the T2080's MDIO register spaces to have information about processor's PCS and auto-negociation.

So, I have defined four new addresses, one for each port's MAC, assigning 0x2 to 0x5 into each MDEV_PORT field (in E_A6C4, E_A6D4, E_A6E4 and E_A6F4 : XFIx Protocol Control Register 1) .

Nevertheless, I cannot acces to MAC MDIO register spaces after this configuration : all accesses always return 0xffff.

=> Which configuration should be performed to access to these registers ?

Best regards,

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r8070z
NXP Employee
NXP Employee


Have a great day,

There are MDIO for each Ethernet controller (MAC) and MDIO for external PHY management. I.e. each MAC has own MDIO to access PCS. Ensure that you use right MDIO for given PCS. For example according to Table 19-1 “. SerDes Lanes Assignments and Multiplexing “ in the reference manual MAC1 controls XFI on Serdes1 lane B. Details of access to MAC1 MDIO you should see in QorIQ T2080 Data Path Acceleration Architecture (DPAA) Reference Manual. It is available on the nxp site
https://www.nxp.com/webapp/Download?colCode=T2080DPAARM

It names MDIO for XFI1 as MDIO-1 for EMAC1 and provides offset of the corresponding MDIO registers including MDIO_CTL register.
The XFIn PCS register space is selected when the associated XFInCR1[MDEV_PORT] matches the Ethernet MAC port address (MDIO_CTL[PORT_ADDR]) and the device address (MDIO_CTL[DEV_ADDR]) is 03h.

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r8070z
NXP Employee
NXP Employee


Have a great day,

There are MDIO for each Ethernet controller (MAC) and MDIO for external PHY management. I.e. each MAC has own MDIO to access PCS. Ensure that you use right MDIO for given PCS. For example according to Table 19-1 “. SerDes Lanes Assignments and Multiplexing “ in the reference manual MAC1 controls XFI on Serdes1 lane B. Details of access to MAC1 MDIO you should see in QorIQ T2080 Data Path Acceleration Architecture (DPAA) Reference Manual. It is available on the nxp site
https://www.nxp.com/webapp/Download?colCode=T2080DPAARM

It names MDIO for XFI1 as MDIO-1 for EMAC1 and provides offset of the corresponding MDIO registers including MDIO_CTL register.
The XFIn PCS register space is selected when the associated XFInCR1[MDEV_PORT] matches the Ethernet MAC port address (MDIO_CTL[PORT_ADDR]) and the device address (MDIO_CTL[DEV_ADDR]) is 03h.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------

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xabiven
Contributor II

Hello Serguei,

I didn't see the individual MDIO "buses". Your explanation associated to table 5-17 of the T2080DPAARM is very clear.

Accesses are now working.

Thanks a lot for your quick answer.

Best regards

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