Hi,
This is the first time I am working with the processor. I have a few doubts about IFC data and address configuration.
I am using 16bit data width NOR Flash with 256MB, the same flash used as a booting device. And for AD pins de-latching, I am using FPGA.
As Processor AD(0:15) pins carry the MSB bits of the address, I will connect those signals to Flash A(0:15) and Processor A(16:26) pins connect to flash A(16:26).
What about the other processor A(27:31) bits, is it has to NC or should be connected/ If it has to be connected where I should connect?
And I need clarity about when we need ADDRESS Shifting and which ADDR_SHIFT_MODE to be used in our case.
Please respond as soon as possible
Thank You
Harika
