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The T2080 data sheet says that IFC_NDDDR_CLK IFC (pin D18) is NAND DDR Clock. I.e. it looks like clock for NAND flash devices using source synchronous DDR mode. However according to the T2080 data-sheet and reference manual there is not support for NAND synchronous DDR mode on the T2080.
High-speed NAND flash may operate in the asynchronous mode and synchronous DDR mode. It is supposed that the same flash device pin is write enable (WE) input for the asynchronous and CLK input for the synchronous mode.
The T2080RDB schematics like first revision of the T2080QDS schematics show that this pin D18 drives NAND flash WE# input. However, the T2080QDS schematics was corrected with corresponding note - now the T2080 IFC_WE (pin D17) drives NAND flash WE input. It corresponds to the T2080 reference manual which says that the IFC_WE provides NAND write enable signal.
The IFC_NDDDR_CLK pin as output can be left open. If you need for comprehensive explanation please create service request - see How I could create a Service Request?
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