T2080 HRESET Is not driving by processor

[Har_ika30]

Hi,

we have one prototype board with a T2080 processor. All power is OK.

Once powered Up, We tried to load the hardcoded RCW, CFG_RCW[0:8] driving from FPGA  before PORESET was released.

Once the Processor samples the Correct RCW it should release the HRESET. In my case, HRESET is driving inconsistently.

So, I am not able to connect to the CodeWarrior tool either. can anyone help me out with this?

Thanks

Harika

[yipingwang]

Table 4-16. RCW Settings for Hard-Coded RCW Options in T2080RM shows two hardcoded values of cfg_rcw_src
1. Please confirm that the correct combination of SYSCLK and cfg_src_src[0:8] is used.
2. Also, what are SD_REF CLK frequencies? Please make sure these are set for hardcoded Serdes PRTCL1 and Serdes PRTCL2 as per the table.
3. Share the scope shot of HRESET, and SYSCLK with respect to PORESET de-assertion.