T2080 DDR3L configuration in QCVS tool

[KL8]

Hello NXP team,

We have a custom T2080 board integrated with DDR3L (part no: IS43TR16K01S2AL-125KBLI) - Discrete DRAM(8GB: 2GBx4)

While performing DDR validation in the CodeWarrior QCVS tool, getting an error as

"Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware!"

Kindly anyone confirm the DDR configuration settings done as below is valid or not

1. Selected "Auto configuration" and "Discrete DRAM"
2. Type = DDR3L
3. DRAM speed Rating = 1600 MT/s
4. Output Data rate = 1600 MT/s
5. Rank/Chip select = 2
6. tCL = 11 clocks (13.8ns)
7. Data bus width = 64 bits
8. DRAM configuration per device = 8Gb: 512Mbx16 (according to our DDR the configuration given in datasheet is 1Gx16 but in QCVS tool there is no option available to configure it to 1Gx16 so we chosen it to 512Mbx16 )

Can we use the 512Mbx16 configuration for 1Gx16 configured DDR??

Thanks & Regards

Kareem

[yipingwang]

the configuration is correct.

Selected "Auto configuration" and "Discrete DRAM"
Type = DDR3
DRAM speed Rating = 1600 MT/s
Output Data rate = 1600 MT/s
Rank/Chip select = 2
tCL = 11 clocks (13.8ns)
Data bus width = 64 bits
DRAM configuration per device = 8Gb: 512Mbx16 (the part is a dual-die chip, 512Mbx16 x 2 = 1Gx16)

user should properly configure the "Start Address" and "Size" for CS0 and CS1 respectively in QCVS.


The error “DDR initialization failed: D_INIT was not cleared by hardware” during QCVS validation typically means the DDR controller never completed its initialization sequence.
the possible causes include:

1. Clock or reset issues
DDR initialization requires stable clocks and proper reset sequencing. If SYSCLK or DDRCLK is unstable or incorrectly strapped, D_INIT will not clear.
Check that DIFF_SYSCLK and PLL ratios match T2080 datasheet requirements.

If DRAM device is held in reset or not properly released, D_INIT will never clear, check DRAM reset signal, user can refer to AN5097 as below:

JEDEC specifications for DDR3/3L/4 UDIMM or discrete DRAM require:
1. DRAM reset signal is asserted for a minimum of 200 μs 2. CKE signal is in logic level low for a minimum of 10 ns before the DRAM reset signal is deasserted 3. CKE signal remains low for a minimum of 500 μs after the DRAM reset signal is deasserted, Figure 18(see AN5097) illustrates these signal timing requirements.

2. Power Rail Sequencing
If DDR power rails or VDD_SOC are not within spec during initialization, the controller cannot complete training.
Ensure all voltages meet T2080 specs before DDR_RESET is released.

3. Incorrect DDR Configuration parameters in QCVS If timing parameters or memory topology settings do not match the DDR device’s datasheet, the controller cannot finish initialization.