T2080 DDR3 MEMORY INTERFACE WITH MICRON DUAL DIE

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T2080 DDR3 MEMORY INTERFACE WITH MICRON DUAL DIE

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rajeshsubramani
Contributor I

Hi,

I am using T2080 processor in my design. In this planned to interface a following MT41K1G8TRF-125 IT E micron memory to the processor DDR3L interface. The above micron part has dual die & a total memory of 8Gbit(4Gbit+4Gbit), each chip has 8bit data width. I am planning to interface 8devices to the processor to meet the 64bit interface plus one additional chip for the ECC. But the selected memory chip has single clock pin dual ODT pins,two clock enable pins & two chip select pins for each indugel die. In this case I have connected clock-0 to all 9 devices. chip select  0&1 is connected to all 9 devices. clock enable 0&1 is connected to all 9 devices. In this I need following clarification: For chip select-1 & clock enable-1 whether the clock-0 is active irrespective chip select ?

Regards,

Rajesh

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lunminliang
NXP Employee
NXP Employee

Hi,

I confirm the answer to the question is YES.

Dual die is exception with one clock pair available for two chip select, CKn would run regardless of the corresponding CKEn or CSn signals are high or low.

Regards

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lunminliang
NXP Employee
NXP Employee

Hi,

From the chip reference manual, it lists the feature supported:

"Programmable support for single-, dual-, and quad-ranked devices and modules"

In JESD79-3F, DDR3 SDRAM Standard, for Stacked/dual-die DDR3 SDRAM x8 Ballout using MO-207, there are two CS, ODT, CKE and one CK pair, your device match this.

Based on above two I assume this is supported, in other words, yes to your question, clock 0 is active. BUT, I need to further confirm this later.

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rajeshsubramani
Contributor I

Hi

Is there any update on this query ?

Regards,

Rajesh

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