T2080 ATMU setup for PCIe1

[scottgerhold]

I have 2 T2080s attached to each other on PCIe. I have 1 setup as the RC and the other setup as the EP. I am only testing traffic (reads/writes) to the EP from the RC. When I run the test for connections between PCIe2 or PCIe4 the test functions correctly and data written to the EP is echoed back correctly on reads from the EP. The test is simply mapping to DRAM on the EP's T2080. So the ATMU registers, LAWs, TLBs are set up correctly.

However, the test fails when using PCIe1. The configuration is exactly the same for all three controller setups. The SW simply is compiled to change the bus from PCIe4 to PCIe1 with appropriate memory changes to the controllers. We have a PCIe analyzer on the bus. We see the writes and reads complete as expected. But the data read back does not represent the data written in the prior step by the RC. When we break in with an emulator from the RC and examine the memory space mapped to the EP DRAM (BAR1) through the PCIe bus, it appears to be a repeating pattern. When I break in to the T2080 EP processor and examine DRAM it is unchanged from the original values written during DRAM init. What is different about PCIe1. I realize that PCIe1 supports SR-IOV, but I do not have that enabled.

[hannahreed36]

The T2080 ATMU setup for PCIe1 looks like an interesting configuration, especially for getting the interface working smoothly. I’d be curious to know if there are any specific settings or checks needed during the setup process. For readers researching related public information Monroe Court Archives may also be worth reviewing. Overall, the setup details here are helpful for anyone working with this type of PCIe configuration.

[jameswilson935]

I ran into something similar while working through a PCIe configuration, and checking the documentation carefully made a big difference. I also compared a few hardware reference details with Pinal Assessor Portal while organizing related information for another project. Hopefully your setup goes smoothly, and I'd be interested to hear what ended up resolving the issue. Thanks for bringing up this topic.

[samuelwhite]

The details shared about the T2080 ATMU setup for PCIe1 provide useful information for anyone exploring hardware configuration and optimization. I found the discussion informative and more related information can be explored through Dallas Assessment Data for additional reference. Tracking configuration methods and technical updates can help improve understanding of system performance. Appreciate the insights shared here and look forward to more discussions on similar topics.

[sophiaanderson]

The T2080 ATMU setup for PCIe1 looks like an interesting configuration topic, especially for those working with system hardware and performance tuning. It is useful to share detailed resources that help users find reliable technical and documentation related information. For additional reference I found Sedgwick Court Hearings helpful for exploring organized public information resources. Clear explanations and shared experiences can make complex setups easier for others to follow and troubleshoot.

[scottgerhold]

I can provide the RC and EP dumps along with the LAW registers. Do you have a specific address range you want for the PCIe interface dumps? Any hidden registers you want (I know they exist as NXP has told us to change a couple in the past). Are you asking for both the normal registers and the PCIe configuration memory space (that is a little harder to get, but I can dump the screen from Lauterbach – which is 98% correct).

I am not sure what exactly you are asking for with the PEX analyzer dumps. If you are just looking for proof that what I said is true (that reads don’t return what was written, I can show that).

[yipingwang]

I can provide the RC and EP dumps along with the LAW registers. Do you have a specific address range you want for the PCIe interface dumps? Any hidden registers you want (I know they exist as NXP has told us to change a couple in the past). Are you asking for both the normal registers and the PCIe configuration memory space (that is a little harder to get, but I can dump the screen from Lauterbach – which is 98% correct).
[NXP] Yes. We want the dumps for the normal registers and the PCIe configuration space. Do this activity for both RC and EP. You may refer to Table 2-5. CCSR Block Base Address Map from T2080RM for PCIe offset. In addition, the register dump of LAW registers is also required.

I am not sure what exactly you are asking for with the PEX analyzer dumps. If you are just looking for proof that what I said is true (that reads don’t return what was written, I can show that).
[NXP] We need PEX analyzer dumps in the failing scenario, i.e., when reads don’t return the written data. It would be great if you also shared analyzer dumps in the passing case to compare.

[scottgerhold]

I can provide the RC and EP dumps along with the LAW registers. Do you have a specific address range you want for the PCIe interface dumps? Any hidden registers you want (I know they exist as NXP has told us to change a couple in the past). Are you asking for both the normal registers and the PCIe configuration memory space (that is a little harder to get, but I can dump the screen from Lauterbach – which is 98% correct).

I am not sure what exactly you are asking for with the PEX analyzer dumps. If you are just looking for proof that what I said is true (that reads don’t return what was written, I can show that).

[yipingwang]

Please provide me the register dumps for PCIe interface, both RC and EP.

Provide the full console logs
PEX analyser dumps

Register dump of LAW registers is also required.