T1042D4RDB SerDes Memory Mapping

[burakorcun_ozka]

Hello,

I'm working with u-boot on T1042D4RDB, and have some question about SerDes memory mapping.

1. Is there a maximum physical memory region which is allocated by CPU for SerDes ? If so, is there any documentation about CPU physical memory mapping limits?
2. If SerDes has a maximum physical memory region, can i set custom size TLBs and LAWs inside this memory region? For example, according to 0x06 SerDes configuration, SerDes has 4 PCIe buses. Can these buses have custom-size memory regions? Is there any constraint about minimum size or maximum size for each bus?
3. Does maximum SerDes memory region depend on CPU or board? I mean, is it configurable size from board to board?

Thanks in advanced.

[ufedor]

Posed questions can't be answered because no "physical memory region is allocated by CPU for SerDes".

Please read QorIQ T1040 Reference Manual, Chapter 2 Memory Map

[burakorcun_ozka]

ufedor,

I'm a little confused and, just wonder that how u-boot know the following addresses for PCIe busses.

	0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
	0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
	0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
	0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
	0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
	0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
	0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
	0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
	0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
	0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
	0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
	0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
	0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
	0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
	0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
	0x0_0000_0000 0x0_ffff_ffff DDR 2GB

These busses are on SerDes lanes, and mem spaces have 256 MB physical memory range.

Can i use an address that is out of 0xC_3FFF_FFFF or 0xC_0000_0000 for a PCIe device? Is 0xC_0000_0000 a start address for busses on SerDes?

Additionally, i didn't see anything about SerDes in Memory Chapter. If there is, could you please tell me a chapter number?

[ufedor]

Please read the QorIQ T1040 Reference Manual, Chapter 28 PCI Express Interface Controller.

You wrote:

> the following addresses for PCIe busses

How these data was obtained in U-Boot?

[burakorcun_ozka]

ufedor,

Are these physical addresses that u-boot uses completely arbitrary? Can i use 0xA_0000_0000 - 0xA_0FFF_FFFF instead of 0xC_0000_0000 - 0xC_0FFF_FFFF for any PCIe device?

I think, statement of SerDes address that starts from 0xC_0000_0000, as i said, is not correct. I mistook.

But, there is still fixed address block in T1042 like boot window only. Is it true?