T1042/T2081 DDR3L mixing onboard and SO-DIMM

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T1042/T2081 DDR3L mixing onboard and SO-DIMM

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kylevonschmacht
Contributor I

Our original plan was to use an array of on-board Ram, with a SO-DIMM for expansion capability. 

With two ranks for on board RAM [MCS0, MCS1], and two for the SO-DIMM [MCS2, MCS3].

Unfortunately the T1042 and T2081 have one one pair [0,1] of the MODT, MCK[+/-], and MCKE signals, which the documentation tells me are supposed to work with the matching MCS[n].

Is this mix doable?  If so how are the clock and ODT signals routed to the ranks?

Thanks for your help,

Kyle von Schmacht

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r8070z
NXP TechSupport
NXP TechSupport


Have a great day,

This mix is not doable. Two rank SO-DIMM require for all possible clocks and ODT outputs of the T2081/T1042 DDR controller, hence in this case there is no room for the on board RAM. I think available 4 chip selects and 2 clock pairs/ODT are suitable for registered DIMM only.

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