T1042 SERDES PLL Lock Time

[deanrametta]

The T1040 Reference Manual (section 4.6.1) describes the device's power on reset sequence. After step 18, there is a note indicating that the software should check that the SERDES PLL has locked. This is indicated by the SerDesx_PLLnRSTCTL[RST_DONE] field. What action should be taken if the verification fails? Should the code allow time for the PLL lock to complete? If so, how long should it take? Thanks in advance for your help.

[ufedor]

After the SerDes PLL is enabled to lock it is needed to wait for 750 us before checking the PLL lock status.

After POR completion the RST_DONE=0 is considered a fatal error and must be corrected by either way:

1) provide correct reference clock for the PLL

2) disable the unused PLL in the RCW.