T1042: GPIO4 not driving the configured o/p ??

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T1042: GPIO4 not driving the configured o/p ??

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jainendra_bahad
Contributor I

RCW[428-429]=01

the o/p state of the following GPIOs remains constant whether they're driven high/low.

GPIO4_15,GPIO4_16,GPIO4_22,GPIO4_23

Direction register  settings :address 0xffe133000, value 0x3da40

1)

Configured O/P

DBG > mem w 0xffe133008 w 0xb734cdf

Memory Write: address 0xffe133008, value 0xb734cdf

Read O/P
DBG > mem r 0xffe133008 w

Memory Read: address 0xffe133008, value 0xb724cdf

2)

Configured O/P

DBG > mem w 0xffe133008 w 0xb73ccdf

Memory Write: address 0xffe133008, value 0xb73ccdf

Read O/P
DBG > mem r 0xffe133008 w

Memory Read: address 0xffe133008, value 0xb724cdf

Direction register  settings :address 0xffe133000, value  0x3d240

3) 

DBG > mem w 0xffe133000 w 0x3d240

Memory Write: address 0xffe133000, value 0x3d240
DBG > mem r 0xffe133000 w

Memory Read: address 0xffe133000, value 0x3d240
DBG > mem r 0xffe133008 w

Memory Read: address 0xffe133008, value 0xb7244df
DBG > mem w 0xffe133008 w 0xb7344df

Configured O/P

Memory Write: address 0xffe133008, value 0xb7344df
DBG > mem r 0xffe133008 w

Read O/P

Memory Read: address 0xffe133008, value 0xb7244df

Configured O/P

Memory Write: address 0xffe133008, value 0xb72c4df

Read O/P
DBG > mem r 0xffe133008 w

Memory Read: address 0xffe133008, value 0xb7244df

Any other external signals are not logically connected to pins of  GPIO4_15,GPIO4_16,GPIO4_22,GPIO4_23.

 

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361 Views
Bulat
NXP TechSupport
NXP TechSupport

Can you read  DCFG_CCSR_RCWSR1 ... DCFG_CCSR_RCWSR16 registers for reviewing?

Regards,

Bulat

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361 Views
jainendra_bahad
Contributor I

Thanks for the response 

Please find the DCFG_CCSR_RCWSR1 ... DCFG_CCSR_RCWSR16 registers values:

Memory Read: address 0xffe0e0100, value 0xc10000e
DBG > mem r 0xffe0e0104 W

Memory Read: address 0xffe0e0104, value 0xe000000
DBG > mem r 0xffe0e0108 W

Memory Read: address 0xffe0e0108, value 0x0
DBG > mem r 0xffe0e010C W

Memory Read: address 0xffe0e010c, value 0x0
DBG > mem r 0xffe0e0110 W

Memory Read: address 0xffe0e0110, value 0x85000000
DBG > mem r 0xffe0e0114 W

Memory Read: address 0xffe0e0114, value 0x400012
DBG > mem r 0xffe0e0118 W

Memory Read: address 0xffe0e0118, value 0xec110000
DBG > mem r 0xffe0e011C W

Memory Read: address 0xffe0e011c, value 0x21000000
DBG > mem r 0xffe0e0120 W

Memory Read: address 0xffe0e0120, value 0x0
DBG > mem r 0xffe0e0124 W

Memory Read: address 0xffe0e0124, value 0x0
DBG > mem r 0xffe0e0128 W

Memory Read: address 0xffe0e0128, value 0x60000000
DBG > mem r 0xffe0e012C W

Memory Read: address 0xffe0e012c, value 0x39000
DBG > mem r 0xffe0e0130 W

Memory Read: address 0xffe0e0130, value 0x0
DBG > mem r 0xffe0e0134 W

Memory Read: address 0xffe0e0134, value 0xd416aa05
DBG > mem r 0xffe0e0138 W

Memory Read: address 0xffe0e0138, value 0x0
DBG > mem r 0xffe0e013C W

Memory Read: address 0xffe0e013c, value 0x0

Regards,

Jainendra

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361 Views
Bulat
NXP TechSupport
NXP TechSupport

You need to set SCFG_QEIOCLKCR = 0x55000000 to get required GPIO4 functionality.

Regards,

Bulat

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