T1040D4RDB - NAND boot mode support

[fdm]

Hi,

The T1040D4RDB board (rev.A schematic V1.0) has the MT29F8G08ABBCAH4:C NAND Flash with 4KB page size and 64 pages per block.

The T1040 Reference Manual (rev.1) doesn't list that NAND configuration in the RCW source encodings table.

Does this board support NAND boot mode or, at least, RCW data read from NAND?

BR,
   Denis

[hitrichard]

Great day!

Where did you find the T1040D4RDB board schematic? I have a T1040D4RDB board but don't have its schematic. Can you send a schematic to my e-mail? My e-mail address is hit_richard@163.com.

Thank you!

[ufedor]

To obtain the schematics please create a Technical Case using your company email - refer to the steps described in:

https://community.nxp.com/thread/381898 

[ufedor]

Sorry, the T1040 RM, "Table 4-6. RCW source encodings" contains various NAND sorces.

[fdm]

Hi Fedor,

I do not see "8-bit NAND Flash, 4 KB page, 64 pages/block" config among them.

[fdm]

I have used the MT29F8G08ADBDAH4 NAND flash chip in my custom T1040-based board currently in production. Unfortunately this chip has EOL status now. Micron recommends MT29F8G08ABBCAH4 part as a replacement. This chip has different configuration ("4 KB page, 64 pages/block" instead of "2 KB page, 64 pages/block"). So I doubt whether successful boot with the new chip is possible.

Would you please confirm that:

• the current T1040D4RDB revision has another flash chip installed (other than MT29F8G08ABBCA),

or

• RCW data read from NAND is possible despite of its internal configuration mismatch?

[ufedor]

Log from the T1040D4RDB:

nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xa3

nand: Micron MT29F8G08ABBCAH4

nand: 1024 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224

It shows that the actual NAND Flash corresponds to the schematics.

Please note that the flash Block size is irrelevant during booting.

The T1040D4RDB is capable to boot from NAND and RCW source is 100010000

[fdm]

Let me ask some further questions to clarify the NAND boot process:

1. Is the "pages/block" parameter also irrelevant during booting?
2. Are page and/or block size parameters irrelevant only when the "ECC disabled" option is selected?
3. Are these parameters irrelevant only to the RCW read and should be overridden early during PBL stage?  T1040 RM says in the "Table 27-4. Description of PBL commands" that the Jump command parameter decoding is page and block size dependent.

[ufedor]

The block-related settings are irrelevant until Block Erase operation is performed.