T1040: chip selects issue in uboot

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T1040: chip selects issue in uboot

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gouravjain
Contributor IV

Hi,

I want to enable some more chip selects from IFC controller. Tried to make changes in u-boot also, but its got hanged.

Here are the changes made by me,

1) T104xRDB.h

#define CONFIG_SYS_RAYCOM1_BASE    0xFF900000

#define CONFIG_SYS_RAYCOM1_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_RAYCOM1_BASE)

#define CONFIG_SYS_CSPR3_EXT    (0xf)

#define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(CONFIG_SYS_RAYCOM1_BASE_PHYS) \

                                | CSPR_PORT_SIZE_8 \

                                | CSPR_MSEL_GPCM \

                                | CSPR_V)

#define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)

#define CONFIG_SYS_CSOR3        0x0

/* RAYCOM1 Timing parameters for IFC CS2 */

#define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \

                                        FTIM0_GPCM_TEADC(0x0e) | \

                                        FTIM0_GPCM_TEAHC(0x0e))

#define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \

                                        FTIM1_GPCM_TRAD(0x1f))

#define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \

                                        FTIM2_GPCM_TCH(0x0) | \

                                        FTIM2_GPCM_TWP(0x1f))

#define CONFIG_SYS_CS3_FTIM3            0x0

2) tlb.c

#ifdef CONFIG_SYS_RAYCOM1_BASE

        SET_TLB_ENTRY(1, CONFIG_SYS_RAYCOM1_BASE, CONFIG_SYS_RAYCOM1_BASE_PHYS,

                      MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,

                      0, 14, BOOKE_PAGESZ_256K, 1),

#endif

3) law.c

#ifdef CONFIG_SYS_RAYCOM1_BASE_PHYS

         SET_LAW(CONFIG_SYS_RAYCOM1_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),

#endif

pls let me know where im doing wrong. Any more configuration is required???

--

Gourav

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yipingwang
NXP TechSupport
NXP TechSupport

Hello Gourav Jain,

What kind of device is configured at IFC CS2? How do you decide IFC Timing parameters for this device?


Have a great day,
Yiping

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gouravjain
Contributor IV

Hi Yiping,

Issue got resolved. It was there because of IFC clock, which was higher than expected for end device.

thanks for you interest in my post..

--

Gourav

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hareeshp
Contributor II

Hi gourav jain,

   Could you please share what you had tried to solve this issue?. Because we are also facing the same issue.

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