T1040 DDR3 ECC Strategy

[adamgarrison]

I am using a 72b DDR3 interface on the T1040.  Using the 72 bit interface normally locks me into using x8 ICs because it only has 8 bits of ECC. What I’m curious about though, would be the possibility of using x16 chips to save space. I could see two possibilities, and I’m just not enough of an expert on SDRAM to know if this would work or just cause more problems than it’s worth. I  would either propose:

   -Use Qty 5 x16 ICs, leaving the upper 8 data bits of the ECC IC unconnected or grounded.

   -Use Qty 4 x16 ICs, and Qty 1 x8 IC for ECC

I’m wondering if either of these schemes would work, and if so, which would be preferred?

 Thank you,

Adam

[r8070z]

Have a great day,

For sure you can use 5 x16 ICs, leaving the upper 8 data bits of the ECC IC unconnected or terminated. Typically unused DQ can be left unconnected while control input like DM should be terminated. You can ask DRAM producer for details. This case is preferred.

You may also use 4 x16 ICs, and 1 x8 IC for ECC if SDRAM organisation and timing of the 16 IS and 8 IS are the same.

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