T1040 DD3L per lane write leveling

[rainerboschung]

Hello,

I am designig a board with T1040. For this desing do not use UDIMM, the SDRAM ar directly placed on the board. the SDRAM chip are placed an routed like a MicroDIMM. And I use SPD.

For me it is not clear how to setup the ddr board options  for my desing. I think I can do this the same way as it is done for the T1040RDB (u-boot ddr.c) but I is not clear how to adapt the per lane write leveling start values (DDR_DDR_WRLVL_CNTL_2/3[WRLVL_START_n]).

How can I determine those values for my design?

As far as I understood this has to be calculated:

WRLVL_START_n = CLK_ADJUST + CLK_propagation_pcb - DQSn_propagation_pcb

Is this correct or how should I calculate this?

Thanks for your support.

Rainer##

[rainerboschung]

In the mean time I received first HW-Prototypes where I applied the write leveling values that have been calculated using the formula I stated above. This works very well.

[r8070z · Accepted solution]

Have a great day,

According to the manual you should also set DDR_WRLVL_CNTL[WRLVL_START] for DQS[0]. It is supposed that by design the DQSn will arrive at the DDR3 memory device before the clock (MCK). During write leveling mode the DRAM controller drives the clock and all DQS signals with initial delays set by WRLVL_START, WRLVL_START_n. . The DQS signal is used by the DDR3 memory device to sample the clock signal.  If the clock signal sampled low, that means that the DQS arrived at the DDR3 memory before the rising clock edge. If sampled high, DQS arrived after the rising clock edge. The DRAM controller will iterate until it sees sampled high, and when that happens the DRAM controller now has established the timing skew between DQS and clock. So the initial values for strobe delay should be suitable for such iteration. Your expression gives rough estimation for initial delay value that should not be exceeded. Notice according to the datasheet even at the controller pins DQS to MCK skew can be greater than one settings step equal to 1/8 clock (245ps/1250ps > 1/8 clock) .  
App. note AN4039 “PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations" says for WRLVL_START: “There are several valid selections for this field. Identify the valid values and select the center value to provide the best margins. For example, if values of 1/2, 5/8, and 3/4 clock delays produce a working DDR interface, a value of 5/8 clock delay should be selected.”

The DDR validation tool can do that for you.

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[addiyi]

Why don't you use DDR validation tool? It will help you to determine the best configuration for your DDR. Take a look on www.nxp.com/qcvs.

Adrian