T1024 boot from NOR flash

[PaulWalker]

When booting from NOR flash, how does Core0 pick-up the boot code?

Board set-up (T1024RDB) is:

Switches set RCW_SRC as NOR flash

PBL/RCW set at BOOT_LOC = NOR flash

But reset state of IFC CS0 has no BA or MASK (all set to zero).

T1024RM says...

"Boot chip-select (CS0) is available at system reset"

"During booting, the IFC registers (including BA_EXT, BA, and AMASK registers)
are modified"

IFC start address for RCW is 0x0000_0000

I assume the IFC finds the RCW at the first address of the NOR flash device on CS0. Is this correct?

PowerPC core reset vector is 0x0_FFFF_FFFC

What does the IFC set for CS0? Does the IFC automatically work out the NOR flash device size, etc.?

Ultimately, how does IFC CS0 map to the core reset vector 0x0_FFFF_FFFC? Is this always the end of the last sector in the NOR flash device on CS0?

I need to know the NOR flash device addresses for programming the RCW and boot program.

Thanks,

[yipingwang]

RCW is programmed at the bottom of NOR flash. For e.g. for a 16MB NOR (0x00_0000 to 0xff_ffff) program at 0x00_0000.
Default Boot Translation window is mapped in 8 Mbytes at 0x0_FF80_0000 to 0x0_FFFF_FFFF. When each core comes out of reset, its MMU has one 4-Kbyte page defined at 0x0_FFFF_Fnnn. First fetch is a burst at 0x0_FFFF_FFE0 and first instruction is executed at 0x0_FFFF_FFFC.
This implies that u-boot should be programmed at top of flash.

[PaulWalker]

Hi,

What I trying to get to the bottom of ...

How does the IFC work out the size of the NOR flash on CS0?  Particularly if all the address lines are not used? There is nothing in RCW that relates to size. Does it read information on the chip?

[yipingwang · Accepted solution]

There is no need for a RCW field to indicate size. PBL will fetch RCW from bottom of flash.

When BOOT_LOC = NOR flash, a default Boot Translation window of 8 megabytes will be created from 0x0_FF80_0000 to 0x0_FFFF_FFF(refer 4.4.3 Boot space translation P.166, RM), and reset vector is mapped to top of flash.

[PaulWalker]

Ok, I think I understand. So the IFC maps top of flash for the boot window, but reads bottom of flash to get RCW. So I just need to map the whole flash device somewhere for writing the top of flash for the boot program and bottom of flash for RCW. Thanks

[RachelGomez123]

Yes, your assumption is correct. When booting from NOR flash, the IFC (Integrated Flash Controller) will look for the Reset Configuration Word (RCW) at the beginning of the NOR flash device on CS0, which is the boot chip-select. The IFC will then load the RCW into the appropriate registers and set up the system configuration accordingly.

At reset, the IFC assumes that the NOR flash device connected to CS0 starts at address 0x0, and it automatically calculates the size of the NOR flash device based on the information in the RCW. The IFC will configure the BA (Base Address) and AMASK (Address Mask) registers to map the NOR flash device to the system memory map.

The PowerPC core reset vector is a fixed address in the system memory map, which is 0x0_FFFF_FFFC for your T1024RDB board. The IFC will map the NOR flash device to the system memory map such that the reset vector address points to the correct location in the NOR flash device. This is typically the last sector of the NOR flash device, but it depends on the size of the NOR flash device and the location of the boot code within it.

To program the RCW and boot program, you need to know the memory addresses of the NOR flash device on CS0. The IFC will automatically map the NOR flash device to the system memory map, so you need to calculate the memory addresses based on the system memory map and the size of the NOR flash device. The exact memory addresses will depend on the size of the NOR flash device and the location of the boot code within it. You can consult the memory map of your T1024RDB board and the datasheet of the NOR flash device to determine the memory addresses.

Regards,

Rachel Gomez

[PaulWalker]

Thanks. My understanding is nearly there ...

"The IFC will map the NOR flash device to the system memory map such that the reset vector address points to the correct location in the NOR flash device"

Given the system memory map reset vector is fixed (0x0_FFFF_FFFC), can I assume the following IFC CS0 behavior, i.e. the last address will always overlay the reset vector?

NOR flash, 16Mbyte: BA = 0xFF00_0000, AM = 0xFF00

NOR flash, 32Mbyte: BA = 0xFE00_0000, AM = 0xFE00

NOR flash, 64Mbyte: BA = 0xFC00_0000, AM = 0xFC00

Thus can I assume IFC_CSPR0, IFC_AMASK0 are already set at code entry on core0?

And finally, ...

If my board does not present the whole flash memory range to the processor, how does the IFC know what portion of the flash memory to map? For example, the VBANK feature on T1040D4RDB switches 16MB portions of a 128MB flash device to the IFC. How does the IFC know to only map 16MB for CS0, even though the JEDEC info of the device says 128MB?

P.S. I am writing the boot program for my board, so I need to know the small details.

Kind regards,