T1024 UCC UART mode no activity

[PaulWalker]

Hi,

I'm working with a T1024-based board that is to use the Quicc UCC in slow UART mode for serial communication with a local FPGA.  The method I am using is from a P-series board that also uses the Quicc UCC(s) and works ok. For the T-series board I am not getting any comms.

My RCW and UCC set-up seems ok but I cannot see any activity when I send data to the pins or use a loopback mode. I have monitored the RxBD chain and there appears to be no activity (all BDs are empty). QE base is set to 0xfe140000 and the UCC1 base is set to 0xfe142000 as per QEIWRM. For the parameter RAM I am using the assign-for-device method to allocate a block of multi-user RAM from the 0xFE150000 block.

I am loading the QE mircocode 'iram_Type_A_T1024_r1.0.bin' from 'github.com/nxp-qoriq/qoriq-qe-ucode'

I don't understand why I am not seeing any activity in the BDs. The Rx is enabled and the RCW TDMA pin muxing is set for UC1/BRG1. I've confirmed the BRG1 set-up is ok. Is there anyway to check if the microcode is running ok? Is the microcode file the correct one to use for the UCCs?

Thanks for any help.

Kind regards,

[Oswalag]

Hello,

The QE Microcode is correct, can you please share more information about the rcw configuration and the pin mux you selected with the pins involved with the UCC configuration, also please share a log file in .txt when the board boot-up to review it.

[PaulWalker]

Please note, the RCW was generated using the QCVS tool. Relevant settings as below:

RCW source is SPI, boot from IFC

SYS_PLL is 400MHz, low speed mode

Core(s) are 600MHz (1/2 PLL)

UC1/UC3 flow control is disabled

QE_TDMA/B = 010 (enable QE UCC pins)

DVDD = 3.3V

[PaulWalker]

Hi,

RCW config is as below from the DCFG registers.

0xfe0e0100: 0c100012 00000000 00000000 11000000 *................*
0xfe0e0110: 00000003 00c00002 4c027000 20002000 *........L.p. . .*
0xfe0e0120: 00000000 00000000 00000000 0002b802 *................*
0xfe0e0130: 00000000 494a5a09 00000000 00000006 *....IJZ.........*

The GPIO4 pins (QE pins) are all default (at reset value). This is ok for the pins for Rx mode. The Rx is operating as null modem (without flow control).

What other registers are of interest?

Note the board is running VxWorks 6.9 so the boot info is not interesting. 

[Oswalag]

Have you tried to test the functionality of the UCC UART with the BSP from NXP?

Unfortunately we don't provide support for WindRiver Software as in your case, I highly recommend you to ask them if the issue could be related to a wrong software configuration. 

[PaulWalker]

Regarding RCW, we have noted in the QCVS tool changing UC1/UC3_CTSB_CDB_SEL has no effect on the output PBL.bin file. Is this the reason the UCC is not working - it is expecting full flow control pins. How do I set-up the UCC for no-flow control? Also, QCVS automatically adds a CRC_CHECK sequence to the PBI data. How do I change the setting without invalidating the CRC? 

[PaulWalker]

This is the content of my RCW/PBI file. Note the highlighted value below - this is bits 320-333. Bits 321 and 322 should be set to 1 according to my QCVS settings for UC1_CTSB_CDB_SEL and UC3_CTSB_CDB_SEL. Note QE_TDMA and QE_TDMB are both set to '010' to enable the UCC pins.

AA55AA55 010E0100 0C100012 00000000 00000000
11000000 00000003 00C00002 4C027000 20002000
00000000 00000000 00000000 0002B802 00000000
494A5A09 00000000 00000006 09125284 20000000
09138000 00000000 08138040 5524B16B

I've tried using the 'Ignore Constraints' mode but this does not give any more control over the setting of these fields.

[PaulWalker]

Hi,

We have confirmed the problem is caused by the incorrect setting for RCW bits 321  (UC1_CTSB_CDB_SEL) bit 322 (UC3_CTSB_CDB_SEL).  I have manually patched the data to set these bits to '1' (i.e. to disable the extra flow control pins), and updated the CRC_Check command. After the system boot, the UCC communication commenced as expected.

It appears the QCVS tool PBL function is ignoring the project settings for UC1_CTSB_CDB_SEL and UC3_CTSB_CDB_SEL.

The tool version used to created the PBL is:

CodeWarrior Development Studio for Power Architecture

Version: 10.5.2
Build: 160608

QorIQ Configuration and Validation Suite

Version 4.5.0
Build: 0001-20160210

[PaulWalker]

Support case 00733363 raised to cover this problem

[PaulWalker · Accepted solution]

The resolution for the support case is that the QCVS tool does not support RCW[UC1_CTSB_CDB_SEL] (bit 321) and RCW[UC3_CTSB_CDB_SEL] (bit 322) for disabling the UCC flow control pins. NXP indicated there are no plans to fix.

To work-around the problem It is necessary to manually patch the RCW binary file and re-calculate any PBI CRC check code. 

Alternatively the UCC flow control pins can be pulled-down in hardware (which achieves the same). The pins to pull-down are TDMA_TSYNC, TDMA_RSYNC and TDMA_RQ (or TDMB as desired). 

Hope this is helpful.

Kind regards,

Paul

[PaulWalker]

For info, I've included some memory dumps of my QE/UCC register set-up. See attached.