T1024 NOR Flash booting stuck, while power up the board-Not always but frequent

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T1024 NOR Flash booting stuck, while power up the board-Not always but frequent

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felixarulrajesh
Contributor I

Hi Experts,

We are using T1024 Processor on our design.

Some time we are facing issues on the NOR Flash booting immediately after power on the board.

The booting stuck and no response on the CLI Console at the PC. On our multiple power on/off trials, at least half of the times we could see this failure cases.While digging more we found few of the below observations. 

Few observations at the board related with this:

1.  Voltage rail seq is as follows:

   On sequence - First - 3.3V,2.5V,1.8V; Second - 1.0V, S1VDD, 1.5V (after 10ms from First); Third - 1.35V & VTT (7ms                                    after 2nd)

   Off Sequence - First - All rails except 1.0V; Second - 1.0V (after 40ms from First)

 

2. 3.3V ramping slowly compare with 1.8V & 2.5V (please refer the attached waveform).We can make the 3.3V ramp faster little more through the regulator CC option, but for 1.8V & 2.5V, we cannot its a fixed. So we may need to live with this. ("...RAMP.png")

3. CPLD, powered by 3.3V, releases all reset lines, once it received a power good (after all power rails crossing its power good and stable high) from the sequencer. There is a 3.3V to 1.8V conversion for the CPU_RESET_L. Due to the 1.8V faster ramp, we are seeing a spikes on the CPU_RESET_L, before a stable reset release. Please refer the attached wavefrom & circuit(CPU_RESET.png, All_resets.png). Would this be one of the reasons for the booting stuck?

4. HRESET is always low when the booting is not happening. Also the buffer control signal BCTL is low.

Is it what expected? While booting is properly happening, i could see a High on both HRESET and BCTL pins.

5. Attached the Reset sequence waveform both for the Boot pass and fail conditions."..._RST-SEQ_bootfails.png", "..._RST-SEQ_bootpass.png"

We are trying to find the root cause for this booting stuck while power up.

Kindly give your valuable input on this issues.

Regards,

Felix.

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sureshk
Contributor II

Hi felixarulrajeshfrancis

      I am also fcing same issue with T1024 design. Processor was hanging some times after power ON some times (sleep siganl is high) .It eas happening very few times immediately after power ON .

     We followed the same power sequencing suggetsed by User manual. : 

        (5ms)First - 3.3V,2.5V,1.8V; Second - 1.0V, S1VDD (after 10ms from First); Third - 1.35V & VTT (10ms                                    after 2nd)

Later we cahnged the sequencing to ( moved core to first): 

(5ms)First - 1.0V, S1VDD 3; Second -  .3V,2.5V,1.8V(after 10ms from First); Third - 1.35V & VTT (20ms                                    after 2nd) 

  Still issue was not resolved but hanging frequncy was came down.

Did you resolve this issue?

 Help us in solving this issue.

Regards,

   suresh K

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felixarulrajesh
Contributor I

Hi Suresh,

We debug this issues in multiple direction and I am not remembering them at present. Let me dig the older content and try to support. 

One thing I remember, we have an external drive connection from CPLD for HRESET and we removed this drive connection and pulled the pin high. Also we had so many assembly related issues too at FLASH and CPLD. From the second proto build, we didn't face this issue. So, it could be a combination of both Electrical and Assembly for our case.

Regards,

Felix.

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r8070z
NXP TechSupport
NXP TechSupport

Have a great day,

There are 2 boot diagrams for the fail and success. Both are not good due to the strange HRESET negation after the spike on the PORESET.

Normally the device begins driving HRESET asserted after sampling the assertion of PORESET and does not release it while PORESET is asserted. On PORESET negation device samples the RCW source POR configuration inputs (cfg_rcw_src[0:n]) reads RCW, applies it and at the end release the HRESET.

I think problem related to the spike on the PORESET. Of course I do not know is there is external device which drives the HRESET too. If other external devices do not release HRESET_B, the device reset sequence stalls at this at this point too.

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