T1024 NOR Flash CFG_RCW_SRC Setting

[bltuna]

We have a custom board that has T1024 and a 128 MB x16 NOR Flash. In the Reference Manual, page 1084, it says that address shift value is 5. However, in the cfg_rcw_src field there is no option such 5, only 4, 7, 10 shift values are available. What value should I select for the cfg_rcw_src field?  

[ufedor]

Which revision of the Manual is in question?

I do not see "5" in the Rev.0.

Is there an external address latch for the NOR Flash?

If "yes" - you can refer to the QorIQ T1024 Reference Design Board Quick Start (at QorIQ® T1024 Reference Design Board|NXP):

cfg_rcw_src

000100111: NOR boot mode

(shift 0)

[bltuna]

It's stated in Rev. 0, page 1082

Yes, we use external latch.

In the reference design IFC_A29 and IFC_30 pins are used as address bits, but we use these pins as IFC_RB2 and IFC_RB3, because we have devices more than two on the IFC bus. So, we followed the reference manual while designing our board. Is there a way of booting CPU from NOR flash using the connections on the Reference Manual, Figure 23-9.

[ufedor]

Originally you wrote:

> In the Reference Manual, page 1084, it says that address shift value is 5.

Please consider that the RM example has been given as a generic example. Not specific to this SoC. Just to explain the concept. The RM has the following note:

"NOTE
These figures are intended to be examples only and may show ADDR pins that are not supported."

In the specific case only IFC_A[16:27] are available for addressing purpose. In such case LSb of the system address will appear on A27. Shifting system address by 4 should work. ADM_SHFT should be 4.

> Is there a way of booting CPU from NOR flash using the connections on the Reference Manual, Figure 23-9.

No.

[bltuna]

According to your mesages and reference manual, I assume that the connections for a 128 MB x16 NOR Flash should be like that

Is that right?

[ufedor]

You are right.