Need timing impact on wait of command completion event. The time taken to wait for setting of CMP is consistent for hardware, or it will be changing with variation of environmental factor (temperature or electromagnetic effect) or any other factors?
The above information will be useful to understand deterministic and consistent hardware behavior for a considered Software.
If the time is varying, is there any factor how much it varies?
According to the reply last time, the calculation is right.
Variability is for every frame.
CMP represents the completion of the entire MDIO transaction.
For Clause 22, an MDIO ‘frame’ is either 32 or 64 bits, depending on whether preamble is enabled.
For Clause 45, a transaction may involve one or two frames, depending on whether an address frame is required.
Each bit of a frame takes 1 MDC cycle.
There is time before and after the frame which I would expect to be 1-2 MDC cycles long, +/- 1 MDC cycle.
The variability is due to two factors:
[1] Variable number of platform/2 cycles to next MDC edge (up to 1 MDC cycle)
[2] Variable sampling time when transferring from MDC domain to platform/2 domain (+/- 1 platform/2 clock), since they are async on receive side
The second could also vary with PVT. It would be at most +/- 1 MDC cycle.
Refer T1024DPAARM, Rev0 page number - 6-47
Would you share which document? It's a good idea to share page numbers.