T1024 IFC connection with MRAM(SRAM)

[safeerkt]

Hi ,

We are planning to use QorIQ T1024 processor in one of our design.We want to interface a MRAM(SRAM archit) to the processor through IFC.We have a 4MBit MRAM with 19 address line and 8 data bit.could you please help me with the address and data mapping from processor to the MRAM part? Which all address and DA lines should I use and how should i map it?

Many Thanks,

Safeer.

[safeerkt]

Hi Alexander,

Thank you very much for your support.

Just one more clarification,

In our SRAM part we have 19 address lines.So can I follow the below address mapping?

 T1024 side                            SRAM side

-----------------                        ------------------

ADDR[16:31]                        A[15:0]

AD[12:15]                             A[19:16]

Could you please confirm this?

Many Thanks,

Safeer.

[alexander_yakov]

Yes, I do not see anything incorrect.

[safeerkt]

Thanks Mr.Alexander.

[alexander_yakov · Accepted solution]

Please look T1024 Reference Manual, Figure 23-65 "IFC to 8-bit NOR device interface" for example SRAM-like device connection. Please note reversal mapping - AD[0:7] to D[7:0] and AD[0:15]+ADDR[16:31] to A[31:0].

Have a great day,
Alexander

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