T1024 COP connection

[PaulWalker]

I have a design layout using a T1024 processor. The design uses JTAG/COP for debug/programming. For the JTAG/COP do I need to connect the JTAG/COP to the processor HRESET_B, or can I leave HRESET_B as not-connected? 

The T1 series migration guide (AN5079) says reset assertion should only use PORESET_B, and there is no soft reset. This seems to suggest the processor HRESET_B should not be connected.

The CodeWarrior TAP manual (CWTAPUG) section 9 says COP SRST_B (pin11) 'may' be connected. Does this say pin11 is optional? Will the emulator work correctly if COP SRST_B is not connected?

Kind regards,

Paul

[Oswalag]

Hello, 

Please find in the QorIQ T1024 Family Design Checklist - Chapter 5.21.2 JTAG system-level recommendations: 

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 23. Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions,
as most have asynchronous behavior and spurious assertion gives unpredictable results.

[PaulWalker · Accepted solution]

Thanks,

That's the same diagram as in the T1024 datasheet (chapter 4.5). I've been using this as a reference. What I wanted to know is what the minimum connections are required to support the COP. I have a working board now and have determined that:

HRESET_B must be pulled-up to OVDD (via a 1K resister).

System board reset (from FPGA/CPLD) must be connected to PORESET_B and TRST_B.

COP_HRESET_B must be connected to PORESET_B.

COP_SRESET_B not-connected. 

COP_TRST_B must be connected to TRST_B.

The above arrangement works ok. My original question was about HRESET_B, which I discovered must be either connected to logic or pulled-up. I also discovered the CodeWarrior TAP emulator does not appear to use COP_SRESET_B so can be left not-connected. 

Thanks again.