「4.7.1 Power-On Reset Sequence」excerpt
9. If the IFC's NAND Flash interface is configured as the RCW source, the reset block
instructs the IFC to load a boot block from Flash into the internal buffer RAM of the
IFC. Once complete, the reset block proceeds to instruct the Pre-Boot Loader to
begin reading in RCW data. Note that if the IFC NAND Flash interface reports an
ECC error, the device reset sequence is halted indefinitely, waiting for another
PORESET_B or hard reset.
Is this correct in the interpretation that the CPU stops reading the SPI if there is an error in the RCW (SPI read) data?
