System clock of T1024 with and without external differential termination

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System clock of T1024 with and without external differential termination

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shalakashinde
Contributor I

Hi

I have attached differential system clock's waveform for T1024 processor with and without external 100 ohm differential termination.

Processor claims presence of internal termination.

Which one is correct?

with external 100ohm differential termination:

2.CGEN_PROC_DIFF_SYSCLK_with_100ohm.bmp

without external 100ohm differential termination:

2.CGEN_PROC_DIFF_SYSCLK_without_100ohm.bmp

CLK_OUT without external 100 ohm differential termination at system clock input of processor:

CLK_OUT_without_100ohm.bmp

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fdm
Contributor IV

Shalaka,

How did you pull IFC_OE_B/cfg_eng_use1 and IFC_WP0_B/cfg_eng_use2 config pins during POR?

It seems that these pins should affect internal termination.

BR,

   Denis

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fdm
Contributor IV

Hi Shalaka,

I have similar problem with my T1040-based board (there is a description).

Do you have the SYSCLK (single-ended) connected to the clock source on your board?

BR,

   Denis

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Pavel
NXP TechSupport
NXP TechSupport

Attached file contains oscilloscope diagram of the system clock from the T1024RDB board. This picture shows that external resistor is not needed. There is internal termination in the T1024.

The T1024RDB board uses the 9FGV0641 as clock source.

 

It looks like that layout on your board is not fully correct.

Attached file also contains clock layout from the T1024RDB board.

Check your layout using the following documents:

http://www.nxp.com/assets/documents/data/en/application-notes/AN2582.pdf

See the Section 7.1.1.

 

or

 

http://www.ti.com/lit/an/spraar7f/spraar7f.pdf

 

or

 

http://www.ti.com/lit/an/scaa082/scaa082.pdf


Have a great day,
Pavel Chubakov

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Pavel
NXP TechSupport
NXP TechSupport

What clock driver is used?

What schematic for clock driver connection to the T1024 is used?


Have a great day,
Pavel Chubakov

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shalakashinde
Contributor I

we have used clock generator 5P49V5935B518LTGI.

Schematic is as shown below:

pastedImage_1.png

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Pavel
NXP TechSupport
NXP TechSupport

The T1024 Datasheet contains requirements for system clock of the T1024:

https://www.nxp.com/webapp/Download?colCode=T1024&Parent_nodeId=1395092749751723088298&Parent_pageTy...

 

See the Section 3.6.1 of the T1024 Datasheet. This Section requires that recommended the sysclock voltage is 1.8 V +/- 90 mV.

The shape on the third picture is correct in comparison to the first and the second picture. Spikes on the edges on the third pictures can be corrected using serial termination.

Your pictures show that resistor approximately 25 OHm or 50 OHm are needed for serial termination.  

See attached file about resistors for serial termination.


Have a great day,
Pavel Chubakov

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shalakashinde
Contributor I

Hi Pavel,

Image 2 is input to the processor at diff_sysclk pins.

And image 3 is output from the processor observed at CLK_OUT pin pad for register setting made so as to replicate diff_sysclk at the pad.

So can we take it as acceptable implementation?

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