Serdes I/O configuration in the T2080 device:

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Serdes I/O configuration in the T2080 device:

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rajeshsubramani
Contributor I

Hi,

I am using T2080 processor in my application: As per my application requirement I want  three x4 PCIe & two x1 SATA , how to configure this one using T2080. Whether the above combination is possible ? If yes please send me the register settings for the same.

Regards,

Rajesh

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LPP
NXP TechSupport
NXP TechSupport

Please, see my answer to your previous questions.

Three x4 PCIe & two x1 SATA configuration is not supported.

T2080 can support two x4 PCIe +  x2PCIe + two x1 SATA


Have a great day,
Pavel

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rajeshsubramani
Contributor I

Hi,

Thanks for the reply, I have one more query on the same section:

In the T2080 Integrated Multicore Communications Processor Family Reference Manual, Rev. C.1, 9/2013 page number:1099 (Table 19-2. SerDes Lanes Assignments and Multiplexing) shows the SERDES 1&2 lane mapping  using SRDS_PRTCL_S1 & S2 .

1. In this two parralel tables are given whether shall I select SRDS_PRTCL_S1 & SRDS_PRTCL_S2 independently or I need to select it by considering one complete row ?(For example consider first row in the table if SRDS_PRTCL_S1 is:6C means then automatically should I select 16 for SRDS_PRTCL_S2).

2. What is Per lane PLL mapping in this table what it refers to ?

Regards,

Rajesh

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LPP
NXP TechSupport
NXP TechSupport

1. SRDS_PRTCL_S1 & S2 settings in RM Table 19-2 are not independent. You must use the settings from the same row.

2. T2080 SERDES block provides two independed PLLs (PLL1 & PLL2). "Per lane PLL mapping" column shows assignment of serdes lanes to either PLL1 or PLL2.


Have a great day,
Pavel

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