Secondary Core Reset not happening in T2080RDB

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Secondary Core Reset not happening in T2080RDB

Contributor II


I am trying to boot secondary cores of T2080RDB from RAM.  I use U-Boot 2016.012 for loading my custom software. I have used the following sequence to perform the secondary core reset and release  so that they start executing from my custom secondary_reset code .

1. CCSR relocation - followed the sequence as mentioned in T2080RM .

2. LAW initialization.

3. Disable all caches

4. Disable TimeBase

5. Clear Boot Release Register (BRR)

6. Reset secondary cores via MPIC-PIR followed by sync. Read back MPIC-PIR to ensure it is written . Also issued 15 EOIs to MPIC after performing the write to PIR

7. Setup Boot space translation registers BSTRLH – 0x0 BSTRLL – address of secondary_reset code BSTAR – configured to enable Boot space translation, target ID = 0x10 and window size 4 KB sync Read Back BSTAR to ensure it is written sync

8. Write 1 to corresponding bits in BRR register followed by sync

9. Enable TimeBase .

The secondary cores does not go to Reset state on giving Reset command through MPIC-PIR register. and hence I am unable to perform the release of secondary cores from my code. 

Please suggest what might have gone wrong. 



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NXP TechSupport
NXP TechSupport

The T2080 manual in section Processor initialization register (MPIC_PIR) says:
For proper system operation, a core should be reset in this way only if the core is already in nap or sleep state. Because a core in either state cannot perform the necessary write to cause a hard reset, a core cannot put itself into hard reset.

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