Remapping NOR Flash address in T1040D4RDB UBOOT

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Remapping NOR Flash address in T1040D4RDB UBOOT

Contributor III



I'm trying to relocate default NOR Flash mapping in T1040D4RDB Uboot from 0xe8000000 to 0xF0000000. So as per the suggestion given in one of the post in NXP community, I modified CONFIG_SYS_FLASH_BASE as 0xF0000000, CONFIG_SYS_FLASH_BASE_PHYS as 0xFF0000000, CONFIG_SYS_TEXT_BASE as 0xF7F40000 and CONFIG_RESET_VECTOR_ADDRESS as 0xF7FFFFC. 


I'm using uboot 2019.07 from DENX git repo.


I have also added TLB and LAW entry for NOR flash.

TLB : VIRT=0xF0000000, PHYS=0xFF000000, SIZE=256MB

LAW: ADDR=0xFF000000, SIZE=256MB


After i flash and try to boot the uboot nothing is printed on the console. 

Is there anything else I need to configure? 

One thing I noticed in reginfo output in normal uboot (with flash @ 0xE8000000) is that, even though I'm setting CONFIG_SYS_FLASH_BASE as 0xE8000000 the TLB entry is mapped from 0xE0000000, why is it so?

reginfo outlet:

TLBCAM entries
entry 00: V: 1 EPN 0xfffff000 RPN 0x7ffff000 size:4 KiB
entry 01: V: 1 EPN 0xfe000000 RPN 0xffe000000 size:16 MiB
entry 02: V: 1 EPN 0xe0000000 RPN 0xfe0000000 size:256 MiB
entry 03: V: 1 EPN 0x80000000 RPN 0xc00000000 size:1 GiB
entry 04: V: 1 EPN 0xf8000000 RPN 0xff8000000 size:256 KiB
entry 05: V: 1 EPN 0xf4000000 RPN 0xff4000000 size:16 MiB
entry 06: V: 1 EPN 0xf5000000 RPN 0xff5000000 size:16 MiB
entry 07: V: 1 EPN 0xf6000000 RPN 0xff6000000 size:16 MiB
entry 08: V: 1 EPN 0xf7000000 RPN 0xff7000000 size:16 MiB
entry 09: V: 1 EPN 0xf0000000 RPN 0xf00000000 size:4 MiB
entry 10: V: 1 EPN 0xff800000 RPN 0xfff800000 size:64 KiB
entry 11: V: 1 EPN 0xffdc0000 RPN 0xfffdc0000 size:256 KiB
entry 12: V: 1 EPN 0x00000000 RPN 0x00000000 size:1 GiB
entry 13: V: 1 EPN 0x40000000 RPN 0x40000000 size:1 GiB
entry 14: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB
entry 15: V: 0 EPN 0x00000000 RPN 0x00000000 size:4 KiB

Local Access Window Configuration
LAWBARH00: 0x0000000f LAWBARL00: 0xe8000000 LAWAR00: 0x81f0001b
        (EN: 1 TGT: 0x1f SIZE: 256 MiB)
LAWBARH01: 0x0000000f LAWBARL01: 0xf4000000 LAWAR01: 0x81800018
        (EN: 1 TGT: 0x18 SIZE: 32 MiB)
LAWBARH02: 0x0000000f LAWBARL02: 0xf6000000 LAWAR02: 0x83c00018
        (EN: 1 TGT: 0x3c SIZE: 32 MiB)
LAWBARH03: 0x0000000f LAWBARL03: 0xffdf0000 LAWAR03: 0x81f00010
        (EN: 1 TGT: 0x1f SIZE: 128 KiB)
LAWBARH04: 0x0000000f LAWBARL04: 0x00000000 LAWAR04: 0x81d00015
        (EN: 1 TGT: 0x1d SIZE: 4 MiB)
LAWBARH05: 0x0000000f LAWBARL05: 0xff800000 LAWAR05: 0x81f0000f
        (EN: 1 TGT: 0x1f SIZE: 64 KiB)
LAWBARH06: 0x0000000c LAWBARL06: 0x00000000 LAWAR06: 0x8000001b
        (EN: 1 TGT: 0x00 SIZE: 256 MiB)
LAWBARH07: 0x0000000f LAWBARL07: 0xf8000000 LAWAR07: 0x8000000f
        (EN: 1 TGT: 0x00 SIZE: 64 KiB)
LAWBARH08: 0x0000000c LAWBARL08: 0x10000000 LAWAR08: 0x8010001b
        (EN: 1 TGT: 0x01 SIZE: 256 MiB)
LAWBARH09: 0x0000000f LAWBARL09: 0xf8010000 LAWAR09: 0x8010000f
        (EN: 1 TGT: 0x01 SIZE: 64 KiB)
LAWBARH10: 0x0000000c LAWBARL10: 0x20000000 LAWAR10: 0x8020001b
        (EN: 1 TGT: 0x02 SIZE: 256 MiB)
LAWBARH11: 0x0000000f LAWBARL11: 0xf8020000 LAWAR11: 0x8020000f
        (EN: 1 TGT: 0x02 SIZE: 64 KiB)
LAWBARH12: 0x0000000c LAWBARL12: 0x30000000 LAWAR12: 0x8030001b
        (EN: 1 TGT: 0x03 SIZE: 256 MiB)
LAWBARH13: 0x0000000f LAWBARL13: 0xf8030000 LAWAR13: 0x8030000f
        (EN: 1 TGT: 0x03 SIZE: 64 KiB)
LAWBARH14: 0x00000000 LAWBARL14: 0x00000000 LAWAR14: 0x00000000
        (EN: 0 TGT: 0x00 SIZE: 2 Bytes)
LAWBARH15: 0x00000000 LAWBARL15: 0x00000000 LAWAR15: 0x81000020
        (EN: 1 TGT: 0x10 SIZE: 8 GiB)

Thanks in advance for all your help.

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6 Replies

NXP TechSupport
NXP TechSupport

Hello Amarnath MB,

The memory map for NOR flash conflicts with BMAN and QMAN.

0xff6000000 0xff7ffffff Queue manager software portal 32 MB
0xff4000000 0xff5ffffff Buffer manager software portal 32 MB

Please refer to the following in include/configs/T104xRDB.h.

#define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
#define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
#define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000

efine CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
#define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
#define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000



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Contributor III

Hi yipingwang,

Thanks for the quick reply.

I have modified BMAN and QMAN mapping as per below

#define CONFIG_SYS_BMAN_MEM_BASE        0xEA000000
#define CONFIG_SYS_BMAN_MEM_PHYS        (0xF00000000ull | CONFIG_SYS_BMAN_MEM_BASE)

#define CONFIG_SYS_QMAN_MEM_BASE        0xEC000000
#define CONFIG_SYS_QMAN_MEM_PHYS        (0xF00000000ull | CONFIG_SYS_QMAN_MEM_BASE)

I have modified DCSRBAR mapping as per below

#define CONFIG_SYS_DCSRBAR                      0xEE000000

#define CONFIG_SYS_DCSRBAR_PHYS          (0xF00000000ull | CONFIG_SYS_DCSRBAR)

I have modified CCSRBARmapping as per below
#define CONFIG_SYS_CCSRBAR                        0x80000000

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NXP TechSupport
NXP TechSupport

Would you please provide your modified header file include/configs/T104xRDB.h to me to do more investigation?

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Contributor III

Hi yipingwang‌,

Please find the attached files.

I have used a macro MSPL_ALTER_NOR_BASE which will enable custom changes.

In working u-boot, why the TLB entry for flash is mapped from 0xE0000000 even though CONFIG_SYS_FLASH_BASE is set as 0xE8000000?

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NXP TechSupport
NXP TechSupport

This is because the TLB entry for NOR flash is define as 256M page, 0xE8000000 is aligned to 0xE0000000.

                      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
                      0, 2, BOOKE_PAGESZ_256M, 1),

For your configuration NOR FLASH is defined as 0xF0000000 to 0xFFFFFFFF, this is conflicted with other devices, please refer to the memory map of the original u-boot.



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Contributor III


I really missed the point about page alignment, thanks for the reply.

I have already disabled PCIe, and NAND in my defconfig. I will test it again with CCSRBAR remapped and CPLD disabled.

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