QorIQ T120 - DDR3 with T Topology

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QorIQ T120 - DDR3 with T Topology

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Contributor I

In our Custom board design using QorIQ T1020 processor we have designed to use T Topology for DDR3 address/command/control and clock groups.

Please confirm whether QorIQ processor supports T Topology for DDR3 as we have seen in some applications notes for DDR design considerations to use fly-by topology.

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NXP TechSupport
NXP TechSupport

Only fly-by topology is supported.

Refer to the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM, Table 1. DDR3 designer checklist:

"31. Ensure fly-by topology is used for address/command/control and clock groups."

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Contributor I

Hi, Thank you for your response and clarity provided.

Due to some design constraints in our custom board design we are not able to met 64 Bit DDR design with fly-by topology.

Since fly-by topology is the only supported/recommended topology, we are planning to design with 32bit DDR; please confirm us the 32 Bit DDR3L configurations to be taken care in our Software configuration as 64Bit is the default configuration in the DDR controller of T1020.

 

Thank You.

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NXP TechSupport
NXP TechSupport

In the QorIQ T1040 Reference Manual, 14.2 DDR Features it is written:

"• Data bus widths supported:
• 64-/72-bit
• 32-/40-bit"

In the 14.4.8 DDR SDRAM control configuration (DDR_DDR_SDRAM_CFG) it is written:

"11–12
DBW
DRAM data bus width.
00 64-bit bus is used.
01 32-bit bus is used.
10 Reserved
11 Reserved"

Additional reference is AN4039_PowerQUICC and QorIQ DDR3 settings, Table 9. DDR_SDRAM_CFG Register field descriptions:

"13

8_BE

8-beat burst enable
0 4-beat bursts are used on the DRAM interface.
1 8-beat bursts are used on the DRAM interface.
...
• If a 32-bit data bus is used, then this field should be set to 1 (8-beat burst)."

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Contributor I

ThanK You..!

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