Hi,
In our current project, we have a link-up problem (PCI Express) with T1024 processor and FPGA (chip to chip). PCIe connection consists of one data-transmission lane (x1, 2.5 GT/s). FPGA and T1024 processors are located very close to each other (Total distance between T1024 and FPGA is 33mm).
The most awkward part is that 5 out 10 boards works without any problem (at 2.5/5 GT/s) while the rest of 10 boards fail to link up.
There is only one 4-output HCSL fanout clock buffer connected to T1024 processor and FPGA references clock pins separately. We checked clock buffer (LMK00334) outputs with oscilloscope and there is no issue (Noise or jitter) with the differential clock.
When we read PCI Express Error Detect Register, it returns no error (Page 1536, T1024RM, Rev. 1).
When we read LTSSM Status Register, it returns x51 (Polling Compliance) error (Page 1515, Table 27-4, T1024RM, Rev. 1).
Increasing rise time of the signal surely increases effects of the reflection. During manufacturing of PCBs and ICs, there are always variations between PCBs and ICs which is the source of tolerance (minimum and maximum ratings). Therefore, we increased data rate up to 5 GT/s to increase the effects of reflections on the boards. But, boards which has no link-up issue at 2.5 GT/s worked successfully at 5 GT/s while the rest failed again. We could not check Tx and RX pairs, since we do not have 12.5GHz or upper bandwidth oscilloscope.
We checked power supply of S1VDD and X1VDD and each one fits between minimum and maximum values given in datasheet (Page 47, Table 4, T1024 Datasheet, Rev 1). There is at most 30mV ripple.
Any one can help me? Any idea is welcome.
Regards,
