MMU TLB table difference for T4160 Target

[vinothkumars]

Hi All,

I am working on T4160RDB board to do MMU setup. I confused with MMU TLB table configuration.

Which one is correct according the DDR and NOR Flash?

init_rev.cmm from Lauterbach Trace32 Script,

;MMU Setup
;NOR FLASH 0xe8000000--0xefffffff (1GB)
MMU.TLB1.Set 0. 0xC0000A00 0xe8000008 0xe8000015 0x00000000 0x00000000
;DDR 0x00000000--0x3fffffff (1GB) 
MMU.TLB1.Set 1. 0xC0000A00 0x00000000 0x00000015 0x00000000 0x00000000

T4240RDB_init_core.tcl from CodeWarrior Flashprogrammer,

# define 256M TLB entry 4 : 0xE0000000 - 0xEFFFFFFF for NOR cache-inhibited, guarded
reg ${CAM_GROUP}L2MMU_CAM4 = 0x9000000A1C08000000000000E000000000000000E0000001

# define MAX_DDR TLB entry 2 : 0x00000000 - 0x7FFFFFFF for DDR cacheable, M
reg ${CAM_GROUP}L2MMU_CAM2 = 0x${DDR_TLB_SIZE}0000041C08000000000000000000000000000000000001

Which one I want to take for Lauterbach Trace32 Script and What could be the issue?

Thanks & Regards,

VinothS

[alexander_yakov · Accepted solution]

Af far as I can see, the difference is in size and offset.

The size should be set to the same value, as the actual size of your memory. For example, if you are using 2Gb DDR memory, than MMU size should be set to 2Gb to use entire memory space. However, if you do not need to use entire memory space, for example if the program you are debugging is less than 1Gb, than you can set MMU size to less value, for example to 1Gb instead of 2Gb, as it is done in your Lauterbach script.

Offset should be also configured the same, as your memory device offset. For example if your NOR flash base address is configured to E0000000 than MMU should be also configured to the same E0000000.

Have a great day,
Alexander
TIC

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