MII to MII direct connection in T1022

[roya_azimi93]

Hi, 

in my custom design, I want to have MII  to MII communication with T1022, 

I have some questions about connection:

1) is MII-MII allowable connection in T1022?

 As i searched and understood, the connection should be as follows:

TXD[0:3] --- RXD[0:3]

RXD[0:3] --- TXD[0:3]

TX_EN --- RX_DV

 RX_DV ---TX_EN

RX_CLK and TX_CLK  must connect to External clock source.

2) how should connect TX_ER and CRS signals?

3) how many nanosecond should I delay between RX_CLK and TX_CLK?

Regars,

Roya

[r8070z]

1) Yes T1022 has MII interface and you can connect MII to MII without phy. You can also read
PHY-Less Ethernet Implementation Using Freescale Power Architecture®Based Microprocessors
https://www.nxp.com/docs/en/supporting-information/WBNR_FTF10_NET_F0568.pdf

2) With a PHYless operation, it is necessary for the transmitting MII to indicate to the receiving MII that the frame is complete and that the data is valid (Rx_DV asserted). This is achieved by connecting the transmitting MII’s Tx_EN signal, which is asserted when the transmitter is sending a frame, to CRS and Rx_DV. 

3) The transmit and receive clocks (Tx_CLK and Rx_CLK respectively) should be driven from the same clock source to limit clock skew and provide correct synchronization between the transmitting and receiving devices.

[roya_azimi93]

Thanks for your response,

I confused about the answer of the third part.

As you noted, don't need delay between RX_CLK and TX_CLK .

But, in the attached document has been emphasized to delay between RX_CLK and TX_CLK because of receiver hold time. 

please help me to resolve this issue. 

Regards

Roya

[roya_azimi93]

Is there any answer please?