Is there a way to boot secondary cores from DDR on T2080?

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Is there a way to boot secondary cores from DDR on T2080?

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amarnathmb
Contributor III

Hi,

I have a custom board with T2080RDB as reference which is booting UBoot (with CONFIG_MP disabled) from NAND. Once uboot boots up on core 0, all other cores are in boot hold-off state. I have loaded vxWorks bootrom image (with SMP support) on to DDR and it works fine on Core 0. Now i want to boot the remaining cores from the same vxWorks bootrom image loaded in DDR, is it possible to do so?

I changed Boot Space Translation Register values to point to vxWorks bootrom image address in DDR, but that didn't help me out. All other cores didn't boot.

Can anyone please clarify me what does the address 0x0_FFFF_Fnnn mean in section 4.3.3 Boot Space Translation of T2080RM Rev 0, 11/2014?

Thanks in advance for all your help...

Regards,

Amar

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r8070z
NXP Employee
NXP Employee

Have a great day,
 

VxWorks may provide multicore processor support. If your VxWorks supports that then core 0 is responsible to configure the system and boot other cores.

When core accesses to some address first this address has to be translated in the core’s MMU to the physical address which should be valid for some local access window (LAW) which routes access to corresponding peripheral, for example to the DDR controller – see chapter “Memory Map Overview” in the T2080RM. Notice now the T2080RM Rev 2 is available on the NXP site.

When core starts to boot its MMU preconfigured for only one 4kB page which translates 0x0_FFFF_000-0x0_FFFF_FFF one to one. Then there is special fixed 8MB boot local window which routes to the boot device. The boot window location starts at address 0x0_FF80_0000 and extends to 0x0_FFFF_FFFF. The boot window has lower priority than other LAWs.

The boot space translation permit to translate this 4kB to any range within first 4GB. If boot translation is to be performed to a 4kB page outside the default boot window (8 MB at 0x0_FF80_0000 to 0x0_FFFF_FFFF) then you also has to prepare the LAW which cover this page and routes to the boot device you selected.

I recommends application note “SMP Boot Process for Dual E500 Cores”
http://www.nxp.com/files/32bit/doc/app_note/AN3542.pdf
It gives more details for the multicore support and boot translation. Do not worry that there are only two cores and it is E500 core. The main ideas even for the boot translation are the same as for the T2080.

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1 Reply
525 Views
r8070z
NXP Employee
NXP Employee

Have a great day,
 

VxWorks may provide multicore processor support. If your VxWorks supports that then core 0 is responsible to configure the system and boot other cores.

When core accesses to some address first this address has to be translated in the core’s MMU to the physical address which should be valid for some local access window (LAW) which routes access to corresponding peripheral, for example to the DDR controller – see chapter “Memory Map Overview” in the T2080RM. Notice now the T2080RM Rev 2 is available on the NXP site.

When core starts to boot its MMU preconfigured for only one 4kB page which translates 0x0_FFFF_000-0x0_FFFF_FFF one to one. Then there is special fixed 8MB boot local window which routes to the boot device. The boot window location starts at address 0x0_FF80_0000 and extends to 0x0_FFFF_FFFF. The boot window has lower priority than other LAWs.

The boot space translation permit to translate this 4kB to any range within first 4GB. If boot translation is to be performed to a 4kB page outside the default boot window (8 MB at 0x0_FF80_0000 to 0x0_FFFF_FFFF) then you also has to prepare the LAW which cover this page and routes to the boot device you selected.

I recommends application note “SMP Boot Process for Dual E500 Cores”
http://www.nxp.com/files/32bit/doc/app_note/AN3542.pdf
It gives more details for the multicore support and boot translation. Do not worry that there are only two cores and it is E500 core. The main ideas even for the boot translation are the same as for the T2080.

-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------