In T1024 based design, what are the scenarios when RESET_REQ_B is asserted and PORESET_B, HRESET_B is de-asserted?

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In T1024 based design, what are the scenarios when RESET_REQ_B is asserted and PORESET_B, HRESET_B is de-asserted?

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shalakashinde
Contributor I

In T1024 based design, what are the scenarios when RESET_REQ_B is asserted and PORESET_B, HRESET_B is de-asserted?

I have a design, where PORESET_B and HRESET_B both are at high logic.

Only RESET_REQ_B is low.

I am not able to load RCW to NOR flash.

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ufedor
NXP TechSupport
NXP TechSupport

> I am not able to load RCW to NOR flash.

Does it mean that there is no valid RCW provided for the processor?

If "yes" - then this is the RESET_REQ_B assertion cause.

General reference - QorIQ T1024 Reference Manual, 7.3.16 Reset Request Status Register (DCFG_CCSR_RSTRQSR1).

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shalakashinde
Contributor I

I have valid RCW for the processor.

And 3 out of 4 boards are working fine.

Only in 1 board, loading RCW to NOR flash is failing.

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ufedor
NXP TechSupport
NXP TechSupport

Use a digital scope to check integrity of the IFC signals connected to the NOR Flash.

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