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There is 8-bit soft reset register RSTCON2 implemented in the CPLD (offset = 11h, CPLD base address = 0xffdf0000). RSTCON2 bit 5 controls that reset signal
PEX_RST
0: No reset occurs.
1: Writing logic 1 produces PCIe x4 slot reset# signal, this bit can auto clear.
This description is from the QorIQ T1040 Reference Design Board User Guide, Rev. 0, 06/2015 available on the NXP site
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