> When the cache is configured as SRAM, this associative logic as still active
> and may consume SRAM memory bandwidth and/or add some random
> latency to SRAM memory accesses.
Your assumption is not correct.
> is there some logic still active and may consume SRAM memory bandwidth
> and/or add some random latency to SRAM memory accesses ？
There are no such logic issues with CPC configured as SRAM.