How to disable some logic when the CPC is configured as SRAM on T4240

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How to disable some logic when the CPC is configured as SRAM on T4240

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Contributor II

I have configured the CPC as SRAM on the T4240 ,

By design, cache block consists of fast cache memory and address associative logic, this logic continuously monitoring bus transactions and perform necessary actions, if any particular memory access hits cache line.

 

When the cache is configured as SRAM, this associative logic as still active and may consume SRAM memory bandwidth and/or add some random latency to SRAM memory accesses.

 

The information on how to disable this logic is not specified in our public documentation, how to disable this logic?

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48 Views
NXP TechSupport
NXP TechSupport

You wrote:

> When the cache is configured as SRAM, this associative logic as still active

> and may consume SRAM memory bandwidth and/or add some random

> latency to SRAM memory accesses.

Your assumption is not correct.

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48 Views
Contributor II

when CPC is configured as SRAM, is there  some logic still active and may consume SRAM  

memory bandwidth and/or add some random latency to SRAM memory accesses ?

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NXP TechSupport
NXP TechSupport

> is there  some logic still active and may consume SRAM memory bandwidth

> and/or add some random latency to SRAM memory accesses ?

There are no such logic issues with CPC configured as SRAM.

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48 Views
Contributor II

当CPC用作SRAM时,是否存在相关逻辑?,能否关闭这些逻辑去降低访问延时,或者是否有其他降低延时的解决方案? 

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