Help me: Why is the HRESET pin of T4240 always low?

[hoverdsp]

HI :

We are developing a product using the T4240, and our hardware design for PORESET and HRESET is as follows:
(1) The PORESET pin of T4240 is externally pulled up with a 4.7K resistor controlled by the CPLD, and the RCW_SRC is also controlled by the CPLD.
(2) The HRESET pin of T4240 is externally pulled up with a 4.7K resistor.

During the debugging process, we encountered a strange phenomenon: the HRESET_B pin remains low at all times. We conducted the following experiments to verify:
(1) We erased all the logic in the CPLD and used the CPU's default values for RCW_SRC, all set to 1. After powering on, we measured the PORESET signal as high, but the HRESET remained low.
(2) The CPLD logic controls the PORESET to generate a reset sequence. Regardless of the RCW_SRC configuration used, the HRESET remains low.

We used an oscilloscope to measure the power-up sequence and power monotonicity of the T4240 and found no issues. The core voltage VDD of the T4240 is 0.998V, and the SYSCLK and DDR CLK are 66M and 133M respectively.

Could you provide suggestions on what might be causing the HRESET to remain low? Thank you very much.

[June_Lu]

For the correct HRESET, please follow the T4240RM, T4240 QorIQ Integrated Multicore Communications Processor Family Reference Manual - Referen..., 4.6.1 Power-on reset sequence, before the step 14, all steps should work correctly. You could test all signals in the Figure 4-1. Power-on reset sequence to check which specific step you are in.

[hoverdsp]

correction : the core voltage 0.993V