ECC configuration in QCVS fails the validation tool

[bitcom]

my ddr configurations works fine in QCVS without ECC enabled. I enabled ecc by setting these two items

ECC(Error Checking and Correction).          Enabled

Accumulated ECC enable.                           yes

However, the validation failed… 

DDR initialization failed : Invalid value at 0xF04 : 0x00001102

and there is a ACE error detection.

I am using 4 of 512MB * 16 bit DDR for memory and 1 of same DDR for 4 bit ECC, our data is 32bit.

I set all the DQ mapping including ECC's to Default, as our layout is 1 to 1 mapping…. 

Is there anything missing.

Thanks

[yipingwang]

Hello liang zhe,

While the DDRv test passes the timing may be slightly different for ECC use. The reference manual indicates which ECC is enabled, all memory accesses are performed on doubled-word boundaries(all DQM signals are set simultaneously). However, when ECC is disabled, the memory system uses the DQM signals for byte lane selection.

Prime DQ signal as defined by JEDEC can be sent via any DQ pin. Micron has selected to send the Prime DQ signal via DQ0, please check whether DQ0 is connected to controller. Other DRAM vendors such as Samsung or Hynix, send the Prime DQ signal in all the pins. Please refer to the following options for this issue.

1. Please connect the prime DQ to the memory controller(one of ECC pins).

2. Disable the write-leveling.

Have a great day,
TIC

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