E5500 Core HID0 Register

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

E5500 Core HID0 Register

751 Views
burakorcun_ozka
Contributor III

Hi,

I'm working on e5500 core, and have a question about HID0 representation difference between e5500 Core RM and BookE.

I'm tracking start.S file in arch/powerpc/cpu/mpc85xx directory of u-boot to learn how to e5500 core is initialized. When u-boot initializes HID0, it configures EMCP, ENMAS7 and TBEN bit(s) of HID0 register. Similarly, BookE has the definition of these HID0 bit(s). However, after i read e5500 Core RM, i noticed that HID0 representation is different than BookE, some bits like ENMAS7 and TBEN aren't available in e5500 Core RM.

TBEN bit of HID0 enables timebase and ENMAS7 bit of HID0 is used for 36-bit addressing. If these bits aren't available in e5500 Core RM, do i have to assume that these bits were already activated?

Thanks in advanced.

Labels (1)
Tags (3)
2 Replies

647 Views
alexander_yakov
NXP Employee
NXP Employee

Sorry for delayed response to this.

Time base is always enabled, and there is no way to disable it via HID0 register, the only way to disable Time Base is to externally assert tben signal by SoC hardware (memory-mapped register). The explanation why it is implemented in this way - is given in E5500 Core Reference Manual, Section 2.8: 

The only enable/disable control over the time base is the TBEN core signal, controlled by the SoC through a memory-mapped register, allowing control of stopping and starting the time base on any core. 

MAS7 register updates are alway enabled. The explanation, why it may be useful to disable it - is given in BookE, description of HID0[EN_MAS7_UPDATE] field: 

Implementations that support this bit do not update MAS7 (upper bits of RPN (RPNU) field) when hardware writes MAS registers via a tlbre, tlbsx, or an interrupt unless this bit is set. This provides a compatibility path for processors that originally offered only 32 bits of physical addressing but have since extended past 32 bits.

As there is no e5500-based processors, that originally offered only 32 bits, maintaining this compatibility is not necessary.

647 Views
burakorcun_ozka
Contributor III

Thank you Alexander for the reply, it is so clear. 

0 Kudos