DDR4 initialization issue in T1022

[debduttabanerje]

In follow up to this post:

https://community.nxp.com/t5/CodeWarrior-for-QorIQ/DDR-single-bit-fault-detected-by-ecc/m-p/1893988/...

As per advice from nxp team, setup a bareboard project with "attach" launch configuration. The ddr controller register was copied (attached).

But the dump format doesn't match with with register export format from qcvs.

Anyway after comparison and modification imported back the registers. and again started validation.

However the result is same.

Now u-boot is stuck where u-boot is copied from spi flash to ddr. (attached)

[williamson1]

Check DDR4 settings: ensure timing, voltage, and speed match the T1022 specs. Update firmware, verify power supply, and test with known-good modules. | NXP  -  paymydoctor

[debduttabanerje]

Dear NXP team,

we are stuck with this problem, please assist.

[yipingwang]

After creating a QCVS DDR project with reading from SPD method.

In properties panel, please configure "DQ mapping - Controller pins" information according to your DDR design schematics.

The DQ_MAPn registers, provide the mapping information of the DRAM DQ order to the controller. controller uses this information during the initialization when training pattern are send and received. when controller does not have or has the wrong map it is not able to perform initialization of DRAM chips.

[Priyanka_Yadav]

Please find attached our DDR4 connector and T1022 schematic pages, there is one is to one mapping in our design. Please suggest what should be the setting value for DQ_MAPn registers in this case.

Thanks...

[debduttabanerje]

As Priyanka said, the mapping from Processor to connector is one is to one.
And from Connector to SDRAM, bit map is as per spd contents Byte 60 to 77. The above dimm is tested and works on some other boards. so the spd bit map must be correct.

[yipingwang]

As you mentioned in https://community.nxp.com/t5/CodeWarrior-for-QorIQ/DDR-single-bit-fault-detected-by-ecc/m-p/1893988/...

>>>No error in ddr initialization in uboot and mtest runs successfully. (see log: uboot_log_mtest.txt)

Please use that configuration.

[debduttabanerje]

Yes, earlier the board was booting up.
We have not many any configuration change from that.
But now it is not booting up and stuck while downloading uboot to ddr from spi flash.

[yipingwang]

Is it possible for you to use the original u-boot image to bringing up the target board?

[debduttabanerje]

While we dont have that u-boot image, we do have the source. So I compiled it and programmed the spi flash with this image.
Unfortunately u-boot is stuck at the same stage.

[yipingwang]

Discussing your current status with the AE team.

[debduttabanerje]

Hi NXP team, any updates?

[yipingwang]

Please refer to the following update from the AE team.

please ask for the following items:

1. please provide the DIMM part number and its corresponding SPD (in text file).
2. lower the data rate on the board to 1200MT/s (by changing the RCW), then see if the DDR works. if it still fails at lower data rate, follow the procedure below, customer can check the code and before MEM_EN = 1  is set, change the registers as stated below.

How to bypass DQ mapping

This is for debug use only.

• The following steps bypasses the DQ mapping. A debug method to determine if DQ mapping is causing the memory controller initialization failure. Or when customer has violated the DQ bit swap rules in their layout.

1) Set the DDR data rate between 1000MT/s and 1200MT/s.

2) Clear all DQn_MAP registers

3) Set the DDR_SDRAM_CFG_2[DDR_SLOW] = 1

4) Set the DEBUG_2[27] = 1, (i.e. 0x1080F04 = 0x10)

[debduttabanerje]

1. Micron 8GB: MTA9ADF1G72AZ-3G2E1. PFA (spd.txt) or spd data read from code warrior (spd_code_warrior_dump.txt)

2. On lowering data rate  to 1200MT/s by changing RCW[MEM_PLL_RAT] = 00_1100, following error comes while booting:

Initializing....using SPD
DDR clock (MCLK cycle 1667 ps) is slower than DIMM(s) (tCKmax 1600 ps) can support.
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
Waiting for D_INIT timeout. Memory may not work.
6 GiB left unmapped
Loading second stage boot loader .................................................................................................

I think the RAM doesn't support speed lower than 1333 MT/s (CL = 11). But since system clock is 100 MHz we can't achieve this speed.

However I tried setting data rate to 1300MT/s i.e  MEM_PLL_RAT to 00_1101. Doing this does not throw any error but still u-boot fails to load from RAM.

Initializing....using SPD
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
WARNING: Calling __hwconfig without a buffer and before environment is ready
6 GiB left unmapped
Loading second stage boot loader .................................................................................................

Since we couldn't lower DDR data rate between 1000 MT/s and 1200 MT/s, I didn't procede with the later part of the exercise. Shall we conduct the experiment with DDR data rate at 1300 MT/s?

[yipingwang]

Confirmed with the AE team, then will be back to you.

[yipingwang]

Please refer to the following update from the AE team.

To bypass DQ mapping

the following needs to be done:

1) Set the DDR data rate between 1000MT/s and 1200MT/s.

2) Clear all DQn_MAP registers

3) Set the DDR_SDRAM_CFG_2[DDR_SLOW] = 1

4) Set the DEBUG_2[27] = 1, (i.e. 0x1080F04 = 0x10)

in your register dump the above register changes are not done.

[debduttabanerje]

The said registers are not there in the dump as I have modified the registers after this dump. Please see my post (of 08-09-2024 02:02 AM) to see the part of the source where I made changes.

Anyway I have now dumped these modified registers and it can be seen in the u-boot log.

[yipingwang]

OK, will be back to you.

[yipingwang]

Please refer to the following update from the AE team.

initially you have said: "8GB DDR4 DIMM from Apacer No error in ddr initialization in uboot and mtest runs successfully."
so the problem in customer board is when they use Micron 8GB: MTA9ADF1G72AZ-3G2E1

can you send me a ccs register dump with Apacer DIMM and the SPD file for the APacer

[yipingwang]

yes you can try it at 1300.

[debduttabanerje]

Tried at 1300 MT/s, these are the changes applied:

1. RCW[0] = 0x0C0D000E

2. Bypassed DQ mapping by adding this lines in drivers/ddr/fsl/fsl_ddr_gen4.c

        /*
         * implement nxp suggested changes
         * to bypass DQ mapping
         * before enabling mem
         */
        // clear all DQn_MAP
        ddr_out32(&ddr->dq_map_0, 0);
        ddr_out32(&ddr->dq_map_1, 0);
        ddr_out32(&ddr->dq_map_2, 0);
        ddr_out32(&ddr->dq_map_3, 0);

        // DDR_SDRAM_CFG_2[DDR_SLOW] = 1
        ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 | 0x00000800);

        // DEBUG_2[27] = 1, (i.e. 0x1080F04 = 0x10)
        // shouldn't it be 0xFE008F04?
        u32 temp32 = ddr_in32(&ddr->debug[1]);
        ddr_out32(&ddr->debug[1], temp32 | 0x10);

        // add some delay in case
        udelay(500);
        // end nxp changes

        /* Let the controller go */
        ddr_out32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
        mb();
        isb();

I had doubt with your suggestion no: 4) Set the DEBUG_2[27] = 1, (i.e. 0x1080F04 = 0x10). Is this address correct? I  tried as shown in above code snippet.

Anyway after making these changes we are getting same problem. (see cngs_ubootLog.txt, #debug was enabled in few source files)

Also I observed that the reg: DDR_ERR_SBE[SBEC] continuously keeps on changing from 0 to ff (see attached screen grab)