DDR3L - T1024 Issue

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DDR3L - T1024 Issue

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Contributor III

We have a board based on the T1024RDB design. The problem that we see is that some udimm modules work on these boards while others do not. The ones that do work need to have different MEM_PLL_RAT setup from the T1024RDB. We have to set it to 0xa to get it to work.

But there is a setting in which multiple modules work. The T1024RDB has the MEM_PLL_RAT set to 16 while the setting on our baord seems to be to set the rcw MEM_PLL_RAT to 7(8 also seems to work but there are some 1 bit EDAC errors which do get corrected) and in the uboot code to fake out the MEM_PLL_RAT to be 16 i.e the DDR Controller registers (from FE008000) are set based on a speed of 1600MTs.

I looked for erratas for the T1024 but could not see any that mentions MEM_PLL_RAT fix where in the RCW could set the DDR PLL to send out the wrong clock.

Any help in figuring out this issue would be very much appreciated. Random trial and error of different combinations seems to take a long time.

Thank you,

Ram Krishnan

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NXP TechSupport
NXP TechSupport

I checked your settings, fully correspond to the T1024RDB. I believe the board should be at least functional at 1600MT/s with the UDIMM taken from the T1024RDB. I think the list of potential problems looks like following:

1. Input or output clocks. As I wrote you need to use a scope to check.

2. Issues with power supplies around DDR. These can be GVDD, VTT,  VREF sources.

3. Issues with DDR3 layout.

Regards,

Bulat

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NXP TechSupport
NXP TechSupport

Can you clarify several questions:

1. What is the SYSCLK/DDRCLK  frequency?

2. Does the board use 240-pin UDIMM as used on the RDB? Or it uses different module type like SODIMM?

3. Do you use the same DDR3 settings as the RDB? If not, what are the settings?

4. What are the RCW values when the board successfully works?

5. Did you follow our DDR3 layout guide during board routing?

Regards,

Bulat

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Contributor III

1. . What is the SYSCLK/DDRCLK  frequency?

>> Both are at a 100M. I set the RCW DDR_REFCLK_SEL to 0 since they both have different sources.

2. Does the board use 240-pin UDIMM as used on the RDB? Or it uses different module type like SODIMM ?

>> Exact same footprint as the T1024RDB eval board. It is a UDIMM. Only difference is that the one we have for our board is a 8G VLP chip for a lower height. But I have tried the two chip modules which are 18KDF1G72AZ-1G6P1 and 18KDF1G72AZ-1G6E1, on the eval board and the eval board comes up. 

3.  Do you use the same DDR3 settings as the RDB? If not, what are the settings?

>> This was our extensive setup. Our Initial setup was the same setting as the RDB which is MEM_PLL_RAT as 0x10 and none of the modules would come up. We have had 3 revs of this board where the layout has been changed and other fixes. This was more in connection with the 10G Marvell chipset, but in Rev-B the layout for the DDR was improved on.  Rev-A and Rev-B boards had the clocks as a single source so the DDR_REFCLK_SEL was set to 1.  Rev-C the clocking was changed to have individual clocks since that was how the eval board was configured. Rev-A boards would only work with  18KDF1G72AZ-1G6E1 and Rev-B boards would only work with  18KDF1G72AZ-1G6P1. For Rev-A the MEM_PLL_RAT was set to 0xE and it would work. But Rev-B we had to set it down to 0xA and it started working.  With Rev-C we were hoping that would all get fixed but it got peculiar. Initially it would only with 18KDF1G72AZ-1G6P1 with a setting of 0xA for the MEM_PLL_RAT , similar to the Rev-B boards. But the software would crash after a day in linux kernel, which it would not crash on the Rev-B board. So we thought it would be the DDR memory issue. Then we started trying all sort of combinations. This involved getting the full register set from the eval board for the DDR controller i.e FE008000 onwards and setting the code in the uboot for exactly those registers (which differed from the eval board). It would start working with the setting of 0x8 and with clk_adjust value of 4 but the uboot is faked out to be mem_pll_rat of 16 in the speed.c file. That seems to work and we have put it in a long term test for now to see if it crashes. It has been 21 hours so far and it is still running (we have DPAA traffic loopback test). It was also works with a MEM_PLL_RAT rcw value of 7 but the clk_adjust has to be changed to 5. The way we can see it behave good is , we have ECC enabled and in the linux kernel we have EDAC enabled. This will give us 1 bits detection and correction. There used to be a whole bunch including in Rev-A and Rev-B board which we ignored because it was working. But with the setting for 8 and uboot setting of 16 and clk_adjust of 4, we do not see those errors on the Rev-C with the 18KDF1G72AZ-1G6P1 module. With the 18KDF1G72AZ-1G6E1 the errors do show up quite a bit , but one thing to note is previously the 18KDF1G72AZ-1G6E1 would not even come up. It would halt at either D_INIT failure or it would crash at the uboot without even coming to the uboot prompt. Even the regular UDIMM from the eval board would work with this setting but with a lot of EDAC 1 bit errors. 

Hopefully the ramble above makes some sense. Please let me know if you need any clarification.

4. What are the RCW values when the board successfully works?

>>> Reset Configuration Word (RCW):
00000000: 0808000e 00000000 00000000 00000000
00000010: 4c800003 80000002 ec027000 21000000
00000020: 00000000 00000000 00000000 00038812
00000030: 00000000 09005a08 00000000 00000006

But for this to work the uboot file arch/powerpc/cpu/mpc85xx/speed.c  has to force the mem_pll_rat in line 162 to be 16 so that the freq_ddrbus is at 1600000000. 

5. Did you follow our DDR3 layout guide during board routing?

>> Yes we did. 

The peculiar thing is that the MEM_PLL_RAT is set to 8 which is exactly half but the uboot is faked to 16. If we just set the MEM_PLL_RAT rcw to be 8 , it will not come up. The reason I started looking at this train of thought is there was a problem that was fixed for 2080 Chip version 1.1 which would take the correct value for he MEM_PLL_RAT. Version 1.0 was cutting it down by half. I was wondering if there might be such an issue of some of other setting that I don't have properly configured.

Thanks for the Prompt Reply,

Ram Krishnan

 

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NXP TechSupport
NXP TechSupport

Some statements like "clk_adjust value of 4" look strange, can you read DDR register's dump starting  from address FE008000?

Did you check clock signals using a scope? For example DDRCLK and DDR's MCK?

Regards,

Bulat

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Contributor III

Pasted at the end of this message is the register memdump for the ddr controller.  Remember that these values are based on a mem_pll_rat value faked to be 16 in the uboot code while the rcw is actually 8. 

The clk_adjust of 4 is from ddr.c 

struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};

static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{}
};

I believe we did but I will double check on the clocks using a scope. 

DDR REGISTER DUMP

fe008000: 000001ff 00000000 000001ff 00000000 ................
fe008010: 00000000 00000000 00000000 00000000 ................
fe008020: 00000000 00000000 00000000 00000000 ................
fe008030: 00000000 00000000 00000000 00000000 ................
fe008040: 00000000 00000000 00000000 00000000 ................
fe008050: 00000000 00000000 00000000 00000000 ................
fe008060: 00000000 00000000 00000000 00000000 ................
fe008070: 00000000 00000000 00000000 00000000 ................
fe008080: 80044402 80004402 00000000 00000000 ..D...D.........
fe008090: 00000000 00000000 00000000 00000000 ................
fe0080a0: 00000000 00000000 00000000 00000000 ................
fe0080b0: 00000000 00000000 00000000 00000000 ................
fe0080c0: 00000000 00000000 00000000 00000000 ................
fe0080d0: 00000000 00000000 00000000 00000000 ................
fe0080e0: 00000000 00000000 00000000 00000000 ................
fe0080f0: 00000000 00000000 00000000 00000000 ................
fe008100: 010c1000 5011000c bcb48c56 0040c158 ....P......V.@.X
fe008110: e7044000 00401101 00441c70 00980000 ..@..@...D.p....
fe008120: 00000000 0c30030c deadbeef 00000000 .....0..........
fe008130: 02000000 00000000 00000000 00000000 ................
fe008140: 00000000 00000000 00000000 00000000 ................
fe008150: 00000000 00000000 00000000 00000000 ................
fe008160: 00000001 04401400 00000000 00000000 .....@..........
fe008170: 89080600 c675f607 00000000 00000000 .....u..........
fe008180: 00000000 00000000 00000000 00000000 ................
fe008190: 0808090b 0c0d0e0a 00000000 00000000 ................
fe0081a0: 00000000 00000000 00000000 00000000 ................
fe0081b0: 00000000 00000000 00000000 00000000 ................
fe0081c0: 00000000 00000000 00000000 00000000 ................
fe0081d0: 00000000 00000000 00000000 00000000 ................
fe0081e0: 00000000 00000000 00000000 00000000 ................
fe0081f0: 00000000 00000000 00000000 00000000 ................
fe008200: 00001c70 00980000 00001c70 00980000 ...p.......p....
fe008210: 00001c70 00980000 00000000 00000000 ...p............
fe008220: 00000000 00000000 00000000 00000000 ................
fe008230: 00000000 00000000 00000000 00000000 ................
fe008240: 00000000 00000000 00000000 00000000 ................
fe008250: 00000000 00000000 00000000 00000000 ................
fe008260: 00000000 00000000 00000000 00000000 ................
fe008270: 00000000 00000000 00000000 00000000 ................
fe008280: 00000000 00000000 00000000 00000000 ................
fe008290: 00000000 00000000 00000000 00000000 ................
fe0082a0: 00000000 00000000 00000000 00000000 ................
fe0082b0: 00000000 00000000 00000000 00000000 ................
fe0082c0: 00000000 00000000 00000000 00000000 ................
fe0082d0: 00000000 00000000 00000000 00000000 ................
fe0082e0: 00000000 00000000 00000000 00000000 ................
fe0082f0: 00000000 00000000 00000000 00000000 ................
fe008300: 00000000 00000000 00000000 00000000 ................
fe008310: 00000000 00000000 00000000 00000000 ................
fe008320: 00000000 00000000 00000000 00000000 ................
fe008330: 00000000 00000000 00000000 00000000 ................
fe008340: 00000000 00000000 00000000 00000000 ................
fe008350: 00000000 00000000 00000000 00000000 ................
fe008360: 00000000 00000000 00000000 00000000 ................
fe008370: 00000000 00000000 00000000 00000000 ................
fe008380: 00000000 00000000 00000000 00000000 ................
fe008390: 00000000 00000000 00000000 00000000 ................
fe0083a0: 00000000 00000000 00000000 00000000 ................
fe0083b0: 00000000 00000000 00000000 00000000 ................
fe0083c0: 00000000 00000000 00000000 00000000 ................
fe0083d0: 00000000 00000000 00000000 00000000 ................
fe0083e0: 00000000 00000000 00000000 00000000 ................
fe0083f0: 00000000 00000000 00000000 00000000 ................
fe008400: 00000000 00000000 00000000 00000000 ................
fe008410: 00000000 00000000 00000000 00000000 ................
fe008420: 00000000 00000000 00000000 00000000 ................
fe008430: 00000000 00000000 00000000 00000000 ................
fe008440: 00000000 00000000 00000000 00000000 ................
fe008450: 00000000 00000000 00000000 00000000 ................
fe008460: 00000000 00000000 00000000 00000000 ................
fe008470: 00000000 00000000 00000000 00000000 ................
fe008480: 00000000 00000000 00000000 00000000 ................
fe008490: 00000000 00000000 00000000 00000000 ................
fe0084a0: 00000000 00000000 00000000 00000000 ................
fe0084b0: 00000000 00000000 00000000 00000000 ................
fe0084c0: 00000000 00000000 00000000 00000000 ................
fe0084d0: 00000000 00000000 00000000 00000000 ................
fe0084e0: 00000000 00000000 00000000 00000000 ................
fe0084f0: 00000000 00000000 00000000 00000000 ................
fe008500: 00000000 00000000 00000000 00000000 ................
fe008510: 00000000 00000000 00000000 00000000 ................
fe008520: 00000000 00000000 00000000 00000000 ................
fe008530: 00000000 00000000 00000000 00000000 ................
fe008540: 00000000 00000000 00000000 00000000 ................
fe008550: 00000000 00000000 00000000 00000000 ................
fe008560: 00000000 00000000 00000000 00000000 ................
fe008570: 00000000 00000000 00000000 00000000 ................
fe008580: 00000000 00000000 00000000 00000000 ................
fe008590: 00000000 00000000 00000000 00000000 ................
fe0085a0: 00000000 00000000 00000000 00000000 ................
fe0085b0: 00000000 00000000 00000000 00000000 ................
fe0085c0: 00000000 00000000 00000000 00000000 ................
fe0085d0: 00000000 00000000 00000000 00000000 ................
fe0085e0: 00000000 00000000 00000000 00000000 ................
fe0085f0: 00000000 00000000 00000000 00000000 ................
fe008600: 00000000 00000000 00000000 00000000 ................
fe008610: 00000000 00000000 00000000 00000000 ................
fe008620: 00000000 00000000 00000000 00000000 ................
fe008630: 00000000 00000000 00000000 00000000 ................
fe008640: 00000000 00000000 00000000 00000000 ................
fe008650: 00000000 00000000 00000000 00000000 ................
fe008660: 00000000 00000000 00000000 00000000 ................
fe008670: 00000000 00000000 00000000 00000000 ................
fe008680: 00000000 00000000 00000000 00000000 ................
fe008690: 00000000 00000000 00000000 00000000 ................
fe0086a0: 00000000 00000000 00000000 00000000 ................
fe0086b0: 00000000 00000000 00000000 00000000 ................
fe0086c0: 00000000 00000000 00000000 00000000 ................
fe0086d0: 00000000 00000000 00000000 00000000 ................
fe0086e0: 00000000 00000000 00000000 00000000 ................
fe0086f0: 00000000 00000000 00000000 00000000 ................
fe008700: 00000000 00000000 00000000 00000000 ................
fe008710: 00000000 00000000 00000000 00000000 ................
fe008720: 00000000 00000000 00000000 00000000 ................
fe008730: 00000000 00000000 00000000 00000000 ................
fe008740: 00000000 00000000 00000000 00000000 ................
fe008750: 00000000 00000000 00000000 00000000 ................
fe008760: 00000000 00000000 00000000 00000000 ................
fe008770: 00000000 00000000 00000000 00000000 ................
fe008780: 00000000 00000000 00000000 00000000 ................
fe008790: 00000000 00000000 00000000 00000000 ................
fe0087a0: 00000000 00000000 00000000 00000000 ................
fe0087b0: 00000000 00000000 00000000 00000000 ................
fe0087c0: 00000000 00000000 00000000 00000000 ................
fe0087d0: 00000000 00000000 00000000 00000000 ................
fe0087e0: 00000000 00000000 00000000 00000000 ................
fe0087f0: 00000000 00000000 00000000 00000000 ................
fe008800: 00000000 00000000 00000000 00000000 ................
fe008810: 00000000 00000000 00000000 00000000 ................
fe008820: 00000000 00000000 00000000 00000000 ................
fe008830: 00000000 00000000 00000000 00000000 ................
fe008840: 00000000 00000000 00000000 00000000 ................
fe008850: 00000000 00000000 00000000 00000000 ................
fe008860: 00000000 00000000 00000000 00000000 ................
fe008870: 00000000 00000000 00000000 00000000 ................
fe008880: 00000000 00000000 00000000 00000000 ................
fe008890: 00000000 00000000 00000000 00000000 ................
fe0088a0: 00000000 00000000 00000000 00000000 ................
fe0088b0: 00000000 00000000 00000000 00000000 ................
fe0088c0: 00000000 00000000 00000000 00000000 ................
fe0088d0: 00000000 00000000 00000000 00000000 ................
fe0088e0: 00000000 00000000 00000000 00000000 ................
fe0088f0: 00000000 00000000 00000000 00000000 ................
fe008900: 00000000 00000000 00000000 00000000 ................
fe008910: 00000000 00000000 00000000 00000000 ................
fe008920: 00000000 00000000 00000000 00000000 ................
fe008930: 00000000 00000000 00000000 00000000 ................
fe008940: 00000000 00000000 00000000 00000000 ................
fe008950: 00000000 00000000 00000000 00000000 ................
fe008960: 00000000 00000000 00000000 00000000 ................
fe008970: 00000000 00000000 00000000 00000000 ................
fe008980: 00000000 00000000 00000000 00000000 ................
fe008990: 00000000 00000000 00000000 00000000 ................
fe0089a0: 00000000 00000000 00000000 00000000 ................
fe0089b0: 00000000 00000000 00000000 00000000 ................
fe0089c0: 00000000 00000000 00000000 00000000 ................
fe0089d0: 00000000 00000000 00000000 00000000 ................
fe0089e0: 00000000 00000000 00000000 00000000 ................
fe0089f0: 00000000 00000000 00000000 00000000 ................
fe008a00: 00000000 00000000 00000000 00000000 ................
fe008a10: 00000000 00000000 00000000 00000000 ................
fe008a20: 00000000 00000000 00000000 00000000 ................
fe008a30: 00000000 00000000 00000000 00000000 ................
fe008a40: 00000000 00000000 00000000 00000000 ................
fe008a50: 00000000 00000000 00000000 00000000 ................
fe008a60: 00000000 00000000 00000000 00000000 ................
fe008a70: 00000000 00000000 00000000 00000000 ................
fe008a80: 00000000 00000000 00000000 00000000 ................
fe008a90: 00000000 00000000 00000000 00000000 ................
fe008aa0: 00000000 00000000 00000000 00000000 ................
fe008ab0: 00000000 00000000 00000000 00000000 ................
fe008ac0: 00000000 00000000 00000000 00000000 ................
fe008ad0: 00000000 00000000 00000000 00000000 ................
fe008ae0: 00000000 00000000 00000000 00000000 ................
fe008af0: 00000000 00000000 00000000 00000000 ................
fe008b00: 00000000 00000000 00000000 00000000 ................
fe008b10: 00000000 00000000 00000000 00000000 ................
fe008b20: 00008080 80000000 80000000 00000000 ................
fe008b30: 00000000 00000000 00000000 00000000 ................
fe008b40: 00000000 00000000 00000000 00000000 ................
fe008b50: 00000000 00000000 00000000 00000000 ................
fe008b60: 00000000 00000000 00000000 00000000 ................
fe008b70: 00000000 00000000 00000000 00000000 ................
fe008b80: 00000000 00000000 00000000 00000000 ................
fe008b90: 00000000 00000000 00000000 00000000 ................
fe008ba0: 00000000 00000000 00000000 00000000 ................
fe008bb0: 00000000 00000000 00000000 00000000 ................
fe008bc0: 00000000 00000000 00000000 00000000 ................
fe008bd0: 00000000 00000000 00000000 00000000 ................
fe008be0: 00000000 00000000 00000000 00000000 ................
fe008bf0: 00000000 00000000 00020500 00000100 ................
fe008c00: 00000000 00000000 00000000 00000000 ................
fe008c10: 00000000 00000000 00000000 00000000 ................
fe008c20: 00000000 00000000 00000000 00000000 ................
fe008c30: 00000000 00000000 00000000 00000000 ................
fe008c40: 00000000 00000000 00000000 00000000 ................
fe008c50: 00000000 00000000 00000000 00000000 ................
fe008c60: 00000000 00000000 00000000 00000000 ................
fe008c70: 00000000 00000000 00000000 00000000 ................
fe008c80: 00000000 00000000 00000000 00000000 ................
fe008c90: 00000000 00000000 00000000 00000000 ................
fe008ca0: 00000000 00000000 00000000 00000000 ................
fe008cb0: 00000000 00000000 00000000 00000000 ................
fe008cc0: 00000000 00000000 00000000 00000000 ................
fe008cd0: 00000000 00000000 00000000 00000000 ................
fe008ce0: 00000000 00000000 00000000 00000000 ................
fe008cf0: 00000000 00000000 00000000 00000000 ................
fe008d00: 00000000 00000000 00000000 00000000 ................
fe008d10: 00000000 00000000 00000000 00000000 ................
fe008d20: 00000000 00000000 00000000 00000000 ................
fe008d30: 00000000 00000000 00000000 00000000 ................
fe008d40: 00000000 00000000 00000000 00000000 ................
fe008d50: 00000000 00000000 00000000 00000000 ................
fe008d60: 00000000 00000000 00000000 00000000 ................
fe008d70: 00000000 00000000 00000000 00000000 ................
fe008d80: 00000000 00000000 00000000 00000000 ................
fe008d90: 00000000 00000000 00000000 00000000 ................
fe008da0: 00000000 00000000 00000000 00000000 ................
fe008db0: 00000000 00000000 00000000 00000000 ................
fe008dc0: 00000000 00000000 00000000 00000000 ................
fe008dd0: 00000000 00000000 00000000 00000000 ................
fe008de0: 00000000 00000000 00000000 00000000 ................
fe008df0: 00000000 00000000 00000000 00000000 ................
fe008e00: 00000000 00000000 00000000 00000000 ................
fe008e10: 00000000 00000000 00000000 00000000 ................
fe008e20: 00000000 00000000 00000000 00000000 ................
fe008e30: 00000000 00000000 00000000 00000000 ................
fe008e40: 00000000 00000000 00000000 00000000 ................
fe008e50: 00000000 00000000 00000000 00000000 ................
fe008e60: 00000000 00000000 00000000 00000000 ................
fe008e70: 00000000 00000000 00000000 00000000 ................
fe008e80: 00000000 00000000 00000000 00000000 ................
fe008e90: 00000000 00000000 00000000 00000000 ................
fe008ea0: 00000000 00000000 00000000 00000000 ................
fe008eb0: 00000000 00000000 00000000 00000000 ................
fe008ec0: 00000000 00000000 00000000 00000000 ................
fe008ed0: 00000000 00000000 00000000 00000000 ................
fe008ee0: 00000000 00000000 00000000 00000000 ................
fe008ef0: 00000000 00000000 00000000 00000000 ................
fe008f00: 00000000 00000002 00000017 14000c20 ...............
fe008f10: 00000000 00000000 00000000 00000000 ................
fe008f20: 00000000 13001400 15001600 18001900 ................
fe008f30: 1a001b00 17003000 00000000 00000000 ......0.........
fe008f40: 00000000 00000000 00000001 d4000000 ................
fe008f50: 0c000d00 0f000f00 12001300 14001500 ................
fe008f60: 10000000 00000000 00000000 00000000 ................
fe008f70: 00000000 00000000 00000000 00000000 ................
fe008f80: 00000000 00000000 00000000 00000000 ................
fe008f90: 00000000 00000000 00000000 26002400 ............&.$.
fe008fa0: 25002500 24002500 24002400 24000000 %.%.$.%.$.$.$...
fe008fb0: 00000003 0f0f0d10 0f100e0d 0e0d0c0e ................
fe008fc0: 0d0f0d0b 0f0d0d10 0e0f0e0c 0f0f0e10 ................
fe008fd0: 0d0f0e0e 0f0e0d0f 0d0f0e0c 0f0e0d10 ................
fe008fe0: 0e0f0e0c 0e0e0c0f 0d0f0e0c 0e0d0c10 ................
fe008ff0: 0d0e0e0c 0f0e0d0f 0e0f0e0d 00000000 ................

Thank you

Ram

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NXP TechSupport
NXP TechSupport

I checked your settings, fully correspond to the T1024RDB. I believe the board should be at least functional at 1600MT/s with the UDIMM taken from the T1024RDB. I think the list of potential problems looks like following:

1. Input or output clocks. As I wrote you need to use a scope to check.

2. Issues with power supplies around DDR. These can be GVDD, VTT,  VREF sources.

3. Issues with DDR3 layout.

Regards,

Bulat

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Contributor III

We figured out the problem. I was wrong before, we did have a voltage issue. The voltage Vdd going to the DIMM was 1.0V instead of 1.35V as per the requirement. It has been fixed and now it works much better and with the RCW value of MEM_PLL_RAT of 16.  

Thank you for all the help. It was very useful in getting to the bottom of this issue. 

Ram Krishnan

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Contributor III

Bulat,

Sorry for the delay. We had some issues with the DDR validation tool to get the optimal parameters. We check with the scope all the clocks and they are all correct. We checked the voltages and they all seem to be fine too. We did relayout the board but for a different reason (we had some issues with the 10G chip which had very strict guidelines about the board layout). During this process we checked the DDR layout too and corrected a few minor things. 

We ran the DDR validation tool against our board and in the rcw setting with 16 we got an optimal setting for the DDR registers. I tried these DDR initialization registers set and put in the set as is and no luck at all. It still stays in a crashed mode. I used the DDR Operational test  in the validation tool and I executed the Write and Read back test with 4 G of memory and it passes. I have attached the ddr report for the rcw setting with 16.

Please let us know what else we can look at.

Thank you,

Ram Krishnan 

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Contributor III

How would I attach the html ddr report to this conversation ? 

Thanks,

Ram

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