DDR validation tool for the T1024

[ramkrishnan]

We have a board built based on the T1024RDB design. We are having some issues with the DDR memory and I am trying to use the DDRv tool to get the optimal numbers for the DDR. 

This is the first time I am using code warrior and I am using Code Warrior for Linux 10.5.1. I am using the Codewarrior TAP to connect to the JTAG. I have an ethernet cable connected to the TAP and accessing it using an ip address. 

I am able to talk to the TAP from the ccs shell. I run the IDcode.tcl and I get the following output

Configuring TAP Interface....

Configured Connection: cwtap : 10.3.62.1

TDO -----
|
* Device 0 IDCODE: 0682001D Device: FSL T1024 rev 1.x
|
TDI -----

###################################################
#
# configTAP - Redefine TAP interface
#
# scanboard - Scans the target system
# and returns the JTAG IDCode
#
# ir - Loopback test
#
###################################################

I run the ir loopback test and I get the following output

(bin) 78 % ir
0: 0xDCBA987654321001
1: 0xDCBA9876543210FE
2: 0xDCBA9876543210FE
3: 0xDCBA9876543210FE
4: 0xDCBA9876543210FE
5: 0xDCBA9876543210FE
6: 0xDCBA9876543210FE
7: 0xDCBA9876543210FE
8: 0xDCBA9876543210FE
9: 0xDCBA9876543210FE
10: 0xDCBA9876543210FE
11: 0xDCBA9876543210FE
12: 0xDCBA9876543210FE

...

Then I run the following commands in the ccs shell to see if the board reacts to it. I have halted the board in uboot

(bin) 75 % ccs::config_chain t10xx
(bin) 76 % ccs::reset_to_debug

and I do see the board locks up and no reaction until I reset the board. 

The problem I am having is in running the Target Connections on the DDRv tool. I have setup a QorIQ configration Project with the T1024 as the processor and enabled a DDR component. I see the target connections cwtap with 10.3.62.1 as the ip address. But the connectivity pin always has a red cross against it indicating it could not connect to the target. I have turned on log verbose on the ccs but I do not see any logs at all. Consequently the Start Validation and Pause buttons are all grayed out. It uses CDDE to connect to the board.   

I also deleted the DDR component and tried to create one using the READ SPD but it would return an error saying could not connect to target. 

Any help on how to move forward would be much appreciated. Please let me know if you need any more details.

Thank you

Ram Krishnan

[ufedor]

Please check POR levels of the cfg_rcw_src[0:8] (multiplexed on {IFC_AD[8:15], IFC_CLE}) and ensure that selected source contains a valid RCW.

[ramkrishnan]

I connected the JTAG to the T1024RDB eval board and I still get the same error as I do with our board. I try the "Operational DDR test" under Validation and it failed with Configuration Error. I followed the same procedure as I did for our board. I did an md.l fe008000 400 and saved it to a .txt and created a DDR component using  annotated hex import type.

This must be something I am doing wrong in using this tool. Any help in figuring out this would be of great help.

Thanks,

Ram

[ramkrishnan]

I now have it working on the T1024EVAL setup with the DIMM that came with the setup and the DIMM (which is a VLP) that we use. Both of them seem to work with the DDRv tool. For some reason if I use the register setting, it does not work. But if I use the default configuration then it seems to work. For the T1024RDB DIMM which is a 4G DIMM I had to change the speed to 1334MTs to get it to work. But with the VLP DIMM (that is our DIMM) it works with 1600Mts and gives quite a few green cells indicating good configuration. 

But the same VLP DIMM on our board with the same setting does not show any green cells. All brown indicating Configuration Error. 

We are going to check all the clocks again to make sure it is all correct. 

Any pointers on what to look for would be great. 

Thanks,

Ram

[ufedor]

Please check that reset to the DIMM is applied properly.

[ramkrishnan]

There was a problem in the way the COP signals were being handled in the CPLD. It was not tied to anything. The CPLD was changed to follow the T1024 Datasheet - Hardware Design Considerations page 178 and every time the Codewarrior would try to connect to the board it would fully reset and the connection would never happen. We then changed it to not HRESET the processor. This helps in enabling the connection to the board from Codewarrior but it back to the original problem of all cells failing and the logs indicate D_INIT not cleared by hardware. It does certainly look like there is a problem in the way in which the DDR Reset is being done.

Is there a document explaining what the CPLD should be doing. It looks like the T1024RDB CPLD is an unknown and not sure how the CPLD treats the COP_HRESET_B and COP_SRESET_B signals. We can see the Reset architecture in the T1024 Reference Design Board User Guide Figure 2-2 page 13. But it still show the CPLD like a Black box. If you can point us to the right document or vhdl code for that it would be great. 

Thank you,

Ram Krishnan

[ufedor · Accepted solution]

Please create a Technical Case - refer to the:

https://community.freescale.com/thread/381898 

[ramkrishnan]

Thank you Fedor, got the T1024RDB CPLD code and followed that for the using the COP pins to reset the DDR3 and now it works well. I am able to get the DDR validation tool working on our board. 

Ram Krishnan

[hareeshp]

Hi Ram Krishnan,

   Could you please share the changes that you have made, because we are also facing the same issue.

Thank you ,

Hareesh.

[ramkrishnan]

Hello Hareesh,

We had our circuit messed to interface with the JTAG and based on the T1024RDB CPLD we fixed our CPLD and it started. I am not sure if I will be able to put the CPLD in here. But NXP was very quick about sending it once you open a technical case. You can use the above link to open a technical case. We used that as a template to change our CPLD to interface with the JTAG. 

Ram

[hareeshp]

Hi Rama Krishnan,

Thanks for the reply, we also had the same issue with JTAG reset and we have solved it.

[ramkrishnan]

I will check on that. I would take it that AN4039 should be the spec to follow. 

Ram

[ramkrishnan]

Thank you for your prompt feedback.

I was able to overcome the problem by removing the installation and reinstalling the full Codewarrior 10.5.1 and now I am able to talk to the board and the Target Connections come up. I suspect it might have been some configuration and service packs that I might have included to get it to work that might have affected it.  

But now I have a different problem. I am running the DDRv tool and I have centering clock enabled and it runs thru the full test with the different values and all them say "Configuration Error". I am following the procedure in the DDR Valiation Document.

I even tried just the Operation DDR Test and that fails too.

The board does come up and I have it halted it on the uboot. If I do a mtest on the uboot shell it works well. I would assume the Operation DDR Test would work. It tries it 3 times and fails. I have the default i.e the Write-Read-Compare test. 

You had mentioned the RCW is sources. But I have created a QorIQ Configuration Project with just the DDR component.

I tried both Reading the SPD and importing the parameters works right now to create the DDR component and neither of them give good results. 

Where in the setup would I give the RCW. The RCW is in the flash when it boots up. 

Ram

[ufedor]

Please use "md" U-Boot command to dump the DDR controller settings and save log into a text file.

During creation of a new DDRV project import the log from the text file.

[ramkrishnan]

One more data point is the logs from the validation tab

#################### Result for: write_read_compare_test ###### Run 1 #############################

Test was not executed!

Err. capture registers:
0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000000
0xE44, 0x00000000 0xE48, 0x00000000 0xE4C, 0x00000000 0xE50, 0x00000000
0xE54, 0x00000000 0xE58, 0x00010000

Dump:
0xF00, 0x00000000 0xF04, 0x00000000 0xF08, 0x00000017 0xF0C, 0x14000C20
0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000
0xF20, 0x00000000 0xF24, 0x33004600 0xF28, 0x35003700 0xF2C, 0x4A003A00
0xF30, 0x3B003C00 0xF34, 0x17005000 0xF38, 0x00000000 0xF3C, 0x00000000
0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0x11000000
0xF50, 0x0A000B00 0xF54, 0x0B000C00 0xF58, 0x0C000D00 0xF5C, 0x0E000E00
0xF60, 0x08000000 0xF64, 0x00000000 0xF68, 0x00000000 0xF6C, 0x00000000
0xF70, 0x00000000 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000
0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000
0xF90, 0x00000000 0xF94, 0x00000000 0xF98, 0x00000000 0xF9C, 0x00000000
0xFA0, 0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000
0xFB0, 0x00000000 0xFB4, 0x00000000 0xFB8, 0x00000000 0xFBC, 0x00000000
0xFC0, 0x00000000 0xFC4, 0x00000000 0xFC8, 0x00000000 0xFCC, 0x00000000
0xFD0, 0x00000000 0xFD4, 0x00000000 0xFD8, 0x00000000 0xFDC, 0x00000000
0xFE0, 0x00000000 0xFE4, 0x00000000 0xFE8, 0x00000000 0xFEC, 0x00000000
0xFF0, 0x00000000 0xFF4, 0x00000000 0xFF8, 0x00000000 0xFFC, 0x00000000

Data:
0x00000000

--------------------------------------------------------------------
Exception: (<<Error configuring the target! - DDR initialization failed: D_INIT was not cleared by hardware!>>)
--------------------------------------------------------------------
Target system was initialized 0 times and it took 0.000000 seconds.
Target system effective test execution took 0.000000 seconds.

Thanks,

Ram

[ramkrishnan]

That is one of the method I tried I save it to a .txt file and put in the | in the end and imported the file during creation of the DDR component and it still gave the same test results. The operation test fails and the validation also fails with all cells as "Configuration Error".

The other method I tried was to Read the SPD and create the component. That did not work either.

Ram

[ramkrishnan]

Just to make sure I was talking to the memory. I removed the DIMM module and tried the READ SPD method , it did not return anything and I guess it timedout out (Usually it says "SPD Successfully Read!"). I also tried with an invalid value for MEM_PLL_RAT in the RCW (It would hang before uboot prompt with D_INIT message indication memory failed) and again it returned back after a timeout without any message indicating that it failed. Changed the MEM_PLL_RAT value to a valid value and the Read SPD is successful.

Just some data points. 

Ram

[ufedor]

Check that the DDRV project has correct DDR data rate value.

[ramkrishnan]

It is 1600Mts which is supported by the Memory Module. The memory module is a Micron

18KDF1G72AZ-1G6E1.

Ram